Prepared By Nazir (MCA KU)
Contents
1.
Accessing
I/O Devices
2.
Addressing
Modes
3.
Assembly
Language
4.
Asynchronous
DRAM
5.
Synchronous
DRAM
6.
Large
Memories
7.
RamBus
Memory
8.
Read-Only
Memory
9.
Representation
of Floating Number
10.
Basic
Operational Concept
11.
Bus
Structure
12.
Bus
Arbitration
13.
Cache
14.
Performance
Of Cache
15.
Cache
miss and hit
16.
CISC
and RISC
17.
Direct
Memory Access
18.
Representation
of Floating Number
19.
Functional
Units Of a Computer
20.
Hardwired
Control
21.
Micro
Programmed Control
22.
Hierarchy
Of Memory
23.
Mapping
Functions
24.
Memory
Locations And Addresses
25.
Memory
Operations and Management
26.
Numbers
And Arithmetic Operations
27.
Performance
Of a System
28.
Interrupts
29.
Pipelining
30.
Standard
IO Interface
31.
Static
Memories
32.
Instruction
And Instruction Sequencing
Computer Organization Questions and Answers – Accessing I/O Devices
This set of Computer Organisation and Architecture MCQ focuses on
“Accessing I/O Devices”.
1. In memory-mapped I/O…
a) The I/O devices and the memory share the same address space
b) The I/O devices have a seperate address space
c) The memory and I/O devices have an associated address space
d) A part of the memory is specifically set aside for the I/O operation
Answer:
Answer:a
Explanation: Its the different modes of accessing the i/o devices.
2. The usual BUS structure used to
connect the I/O devices is
a) Star BUS structure
b) Multiple BUS structure
c) Single BUS structure
d) Node to Node BUS structure
Answer:
Answer:c
Explanation: BUS is a collection of address,control and data lines used to
connect the various devices of the computer.
3. In intel’s IA-32 architecture
there is a seperate 16 bit address space for the I/O devices..??
a) False
b) True
Answer:
Answer:b
Explanation: This type of accessing is called as I/O mapped devices.
4. The advantage of I/O mapped
devices to memory mapped is
a) The former offers faster transfer of data
b) The devices connected using I/O mapping have a bigger buffer space
c) The devices have to deal with fewer address lines
d) No advantage as such
Answer:
Answer:c
Explanation: Since the I/O mapped devices have a seperate address space
the address lines are limited by amount of the space allocated.
5. The system is notified of a read
or write operation by
a) Appending an extra bit of the address
b) Enabling the read or write bits of the devices
c) Raising an appropriate interrupt signal
d) sending a special signal along the BUS
Answer:
Answer:d
Explanation: It is necessary for the processor to send a signal intimating
the request as either read or write.
6. To overcome the lag in the
operating speeds of the I/O device and the processor we use
a) BUffer spaces
b) Status flags
c) Interrupt signals
d) Exceptions
Answer:
Answer:b
Explanattion: The processor operating is much faster than that of the I/O
devices , so by using the status flags the processor need not wait till the I/O
operation is done. It can continue with its work until the status flag is set.
7. The method of accessing the I/O
devices by repeatedly checking the status flags is
a) Program-controlled I/O
b) Memory-mapped I/O
c) I/O mapped
d) None
Answer:
Answer:a
Explanation: In this method the processor constantly checks the status
flags , and when it finds that the flag is set it performs the appropriate
operation.
8. The method of synchronising the
processor with the I/O device in which the device sends a signal when it is
ready is
a) Exceptions
b) Signal handling
c) Interrupts
d) DMA
Answer:
Answer:c
Explanation: This is a method of accessing the I/O devices which gives the
complete power to the devices, enabling them to intimate the processor when
they’re ready for transfer.
9. The method which offers higher
speeds of I/O transfers is
a) Interrupts
b) Memory mapping
c) Program-controlled I/O
d) DMA
Answer:
Answer:d
Explanation: In DMA the I/O devices are directly allowed to interact with the
memory with out the intervention of the processor and the transfres take place
in the form of blocks increasing the speed of operaion.
10. The process where in the
processor constantly checks the status flags is called as
a) Polling
b) Inspection
c) Reviewing
d) Echoing
Answer:
Answer:a
Explanation: None.
This set of Microprocessor Multiple Choice Questions & Answers
(MCQs) focuses on “Addressing Modes ”.
1. The instruction, MOV AX, 0005H
belongs to the address mode
a) register
b) direct
c) immediate
d) register relative
Answer:
Answer: c
Explanation: In Immediate addressing mode, immediate data is a part of
instruction and appears in the form of successive byte or bytes.
2. The instruction, MOV AX, 1234H
is an example of
a) register addressing mode
b) direct addressing mode
c) immediate addressing mode
d) based indexed addressing mode
Answer:
Answer: c
Explanation: since immediate data is present in the instruction.
3. The instruction, MOV AX, [2500H]
is an example of
a) immediate addressing mode
b) direct addressing mode
c) indirect addressing mode
d) register addressing mode
Answer:
Answer: b
Explanation: Since the address is directly specified in the instruction as a
part of it.
4. If the data is present in a
register and it is referred using the particular register, then it is
a) direct addressing mode
b) register addressing mode
c) indexed addressing mode
d) immediate addressing mode
Answer:
Answer: b
Explanation: Since register is used to refer the address.
5. The instruction, MOV AX,[BX] is
an example of
a) direct addressing mode
b) register addressing mode
c) register relative addressing mode
d) register indirect addressing mode
Answer:
Answer: d
Explanation: Since the register used to refer the address is accessed
indirectly.
6. If the offset of the operand is
stored in one of the index registers, then it is
a) based indexed addressing mode
b) relative based indexed addressing mode
c) indexed addressing mode
d) none of the mentioned
Answer:
Answer: c
Explanation: in indexed addressing mode, the offset of operand is stored and in
the rest of them, address is stored.
7. The addressing mode that is used
in unconditional branch instructions is
a) intrasegment direct addressing mode
b) intrasegment indirect addressing mode
c) intrasegment direct and indirect addressing mode
d) intersegment direct addressing mode
Answer:
Answer: b
Explanation: In intrasegment indirect mode, the branch address is found as the
content of a register or a memory location.
8. If the location to which the
control is to be transferred lies in a different segment other than the current
one, then the mode is called
a) intrasegment mode
b) intersegment direct mode
c) intersegment indirect mode
d) intersegment direct and indirect mode
Answer:
Answer: d
Explanation: In intersegment mode, the control to be transferred lies in a
different segment.
9. The instruction, JMP
5000H:2000H;
is an example of
a) intrasegment direct mode
b) intrasegment indirect mode
c) intersegment direct mode
d) intersegment indirect mode
Answer:
Answer: c
Explanation: since in intersegment direct mode, the address to which the
control is to be transferred is in a different segment.
10. The contents of a base register
are added to the contents of index register in
a) indexed addressing mode
b) based indexed addressing mode
c) relative based indexed addressing mode
d) based indexed and relative based indexed addressing mode
Answer:
Answer: d
Explanation: The effective address is formed by adding the contents of both
base and index registers to a default segment
Computer Organization Questions and Answers – Assembly Language
This set of Computer Organization and Architecture MCQ focuses on
“Assembly language”.
1. ____ converts the programs
written in assembly language into machine instructions .
a) Machine compiler
b) Interpreter
c) Assembler
d) Converter
Answer:
Answer:c
Explanation: The assembler is a software used to convert the programs into
machine instructions.
2. The instructions like MOV or ADD
are called as ______ .
a) OP-Code
b) Operators
c) Commands
d) None of the above
Answer:
Answer:a
Explanation: This OP – codes tell the system what operation to perform on
the operands.
3. The alternate way of writing the
instruction, ADD #5,R1 is ______ .
a) ADD [5],[R1];
b) ADDI 5,R1;
c) ADDIME 5,[R1];
d) There is no other way
Answer:
Answer:b
Explanation: The ADDI instruction, means the addition is in immediate
addressing mode.
4. Instructions which wont appear
in the object program are called as _____ .
a) Redundant instructions
b) Exceptions
c) Comments
d) Assembler Directives
Answer:
Answer:d
Explanation: The directives help the program in getting compiled and hence
wont be there in the object code.
5. The assembler directive EQU,
when used in the instruction : Sum EQU 200 does,
a) Finds the first occurrence of Sum and assigns value 200 to it
b) Replaces every occurrence of Sum with 200
c) Re-assigns the address of Sum by adding 200 to its original address
d) Assigns 200 bytes of memory starting the location of Sum
Answer:
Answer:b
Explanation: This basically is used to replace the variable with a
constant value.
6. The purpose of the ORIGIN
directive is,
a) To indicate the starting position in memory, where the program block is to
be stored
b) To indicate the starting of the computation code
c) To indicate the purpose of the code
d) To list the locations of all the registers used
Answer:
Answer:a
Explanation: This does the function similar to the main statement.
7. The directive used to perform
initialization before the execution of the code is ______ .
a) Reserve
b) Store
c) Dataword
d) EQU
Answer:
Answer:c
Explanation: None.
8. _____ directive is used to
specify and assign the memory required for the block of code .
a) Allocate
b) Assign
c) Set
d) Reserve
Answer:
Answer:d
Explanation: This instruction is used to allocate a block of memory and to
store the object code of the program there.
9. _____ directive specifies the
end of execution of a program .
a) End
b) Return
c) Stop
d) Terminate
Answer:
Answer:b
Explanation: This instruction directive is used to terminate the program
execution.
10. The last statement of the
source program should be _______ .
a) Stop
b) Return
c) OP
d) End
Answer:
Answer:d
Explanation: This enables the processor to load some other process.
11. When dealing with the branching
code the assembler,
a) Replaces the target with its address
b) Does not replace until the test condition is satisfied
c) Finds the Branch offset and replaces the Branch target with it
d) Replaces the target with the value specified by the DATAWORD directive
Answer:
Answer:c
Explanation: When the assembler comes across the branch code, it
immediately finds the branch offset and replaces it with it.
12. The assembler stores all the
names and their corresponding values in ______ .
a) Special purpose Register
b) Symbol Table
c) Value map Set
d) None of the above
Answer:
Answer:b
Explanation: The table where the assembler stores the variable names along
with their corresponding memory locations and values.
13. The assembler stores the object
code in ______ .
a) Main memory
b) Cache
c) RAM
d) Magnetic disk
Answer:
Answer:d
Explanation: After compiling the object code, the assembler stores it in
the magnetic disk and waits for further execution.
14. The utility program used to
bring the object code into memory for execution is ______.
a) Loader
b) Fetcher
c) Extractor
d) Linker
Answer:
Answer:a
Explanation: The program which is used to load the program into memory.
15. To overcome the problems of the
assembler in dealing with branching code we use _____ .
a) Interpreter
b) Debugger
c) Op-Assembler
d) Two-pass assembler
Answer:
Answer:d
Explanation: This creates entries into the symbol table first and then
creates the object code.
Computer Organization Questions and Answers – Asynchronous DRAM
This set of Computer Organisation and Architecture MCQ focuses on
“Asynchronous DRAM”.
1. The Reason for the disregarding
of the SRAM’s is
a) Low Efficiency.
b) High power consumption.
c) High Cost.
d) All of the above.
Answer:
Answer:c
Explanation: The reason for the high cost of the SRAM is because of the
usage of more number of transistors.
2. The disadvantage of DRAM over
SRAM is/are
a) Lower data storage capacities.
b) Higher heat descipation.
c) The cells are not static.
d) All of the above.
Answer:
Answer:c
Explanation: This means that the cells wont hold their state indefinetly.
3.The reason for the cells to lose
their state over time is
a) The lower voltage levels.
b) Usage of capacitors to store the charge.
c) Use of Shift registers.
d) None of the above.
Answer:
Answer:b
Explanation: Since capacitors are used the charge descipates over time.
4. The capacitors lose the charge
over time due to
a) The leakage resistance of the capacitor.
b) The small current in the transistor after being turned off.
c) The defect of the capacitor.
d) Both a and b.
Answer:
Answer:d
Explanation: The capacitor loses charge due to the backward current of the
transistro and due to the small resistance.
5. _________ circuit is used to
restore the capacitor value.
a) Sense amplify
b) Signal amplifier
c) Delta modulator
d) None of the above
Answer:
Answer:a
Explanation: The sense amplifier detects if the value is above or below
the threshlod and then restores it.
6. To reduce the number of external
connections reqiured, we make use of ______.
a) De-multiplexer
b) Multiplexer
c) Encoder
d) Decoder
Answer:
Answer:b
Explanation: We multiplex the various address lines onto fewer pins.
7. The processor must take into
account the delay in accessing the memory location, such memories are called
______.
a) Delay integrated
b) Asynchronous memories
c) Synchronous memories
d) Isochronous memories
Answer:
Answer:b
Explanation: None.
8. To get the row address of the
required data ______ is enabled.
a) CAS
b) RAS
c) CS
d) Sense/write
Answer:
Answer:b
Explanation: This makes the contents of the row required refreshed.
9. In order to read multiple bytes
of a row at the same time, we make use of ______.
a) Latch
b) Shift register
c) Cache
d) Memory extension
Answer:
Answer:a
Explanation: The latch makes it easy to ready multiple bytes of data of
the same row simulteneously by just giving the consecutive column address.
10. The block transfer capability
of the DRAM is called ________.
a) Burst mdoe
b) Block mode
c) Fast page mode
d) Fast frame mode
Answer:
Answer:c
Explanation: None.
Computer Organization Questions and Answers – Synchronous DRAM
This set of Computer Organisation and Architecture MCQ focuses on
“Synchronous DRAM”.
1. The difference between DRAM’s
and SDRAM’s is/are
a) The DRAM’s make use of the master slave relationship in data transfer.
b) The SDRAM’s make use of clock.
c) The SDRAM’s are more power efficient.
d) Both a and b
Answer:
Answer:d
Explanation: The SDRAM’s make use of clock signals to synchronise their
operation.
2. The difference in address and
data connection between DRAM’s and SDRAM’s is
a) The usage of more number of pins in SDRAM’s.
b) The requirement of more address lines in SDRAM’s.
c) The usage of buffer in SDRAM’s.
d) None of the above.
Answer:
Answer:c
Explanation: The SDRAM uses buffered storage of address and data.
3. A _______ is used to restore the
contents of the cells.
a) Sense amplifier
b) Refresh counter
c) Restorer
d) None of the above
Answer:
Answer:b
Explanation: The Counter helps to restore the charge on the capacitor.
4. The mode register is used to
a) Select the row or column data transfer mode.
b) Select the mode of operation.
c) Select mode of storing the data.
d) All of the above.
Answer:
Answer:b
Explanation: The mode register is used to choose between burst mode or bit
mode of operation.
5. In a SDRAM each row is refreshed
every 64ms.
a) True
b) False
Answer:
Answer:a
Explanation: None.
6. The time taken to transfer a
word of data to or from the memory is called as ______.
a) Access time
b) Cycle time
c) Memory latency
d) None of the above
Answer:
Answer:c
Explanation: The performance of the memory is measured by means of
latency.
7. In SDRAM’s buffers are used to
store data that is read or written.
a) True
b) False
Answer:
Answer:a
Explanation: In SDRAm’s all the bytes of data to be read or written are
stored in the buffer until the operation is complete.
8. The SDRAM performs operation on
the _______.
a) Rising edge of the clock
b) Falling edge of the clock
c) Middle state of the clock
d) Transition state of the clock
Answer:
Answer:a
Explanation: The SDRAM’s are edge-triggered.
9. DDR SDRAM’s perform fster data
transfer by
a) Integrating the hardware.
b) Transfering on both edges.
c) Improving the clock speeds.
d) Increasing the bandwidth.
Answer:
Answer:b
Explanation: By transfering data on both the edges the bandwidth is
effectively doubled.
10. To improve the data retrieval
rate
a) The memory is divided into two banks.
b) The hardware is changed.
c) The clock frequency is increased.
d) None of the above.
Answer:
Answer:a
Explanation: The division of memory into two banks makes it easy to access
two different words at each edge of the clock.
Computer Organization Questions and Answers – Large Memories
This set of Computer Organisation and Architecture MCQ focuses on
“Large Memories”.
1. The chip can be disabled or cut
off from external connection using ______.
a) Chip select
b) LOCK
c) ACPT
d) RESET
Answer:
Answer:a
Explanation: The chip gets enabled if the CS is set otherwise the chip
gets disabled.
2. To organise large memory chips we
make use of ______.
a) Integrated chips
b) Upgraded hardware
c) Memory modules
d) None of the above
Answer:
Answer:c
Explanation: The cell blocks are arranged and put in a memory module.
3. The less space consideration as
lead to the development of ________ (for large memories).
a) SIMM’s
b) DIMS’s
c) SSRAM’s
d) Both a and b
Answer:
Answer:d
Explanation: The SIMM (single inline memory module) or DIMM (dual inline
memory module) occupy less space while providing greater memory space.
4. The SRAM’s are basically used as
______.
a) Registers
b) Caches
c) TLB
d) Buffer
Answer:
Answer:b
Explanation: The SRAM’s are used as caches as their opeartion speed is
very high.
5. The higher order bits of the
address are used to _____.
a) Specify the row address
b) Specify the column address
c) Input the CS
d) None of the above
Answer:
Answer:a
Explanation: None.
6. The address lines multiplexing
is done using ______.
a) MMU
b) Memory controller unit
c) Page table
d) Overlay geberator
Answer:
Answer:b
Explanation: This unit multiplexes the various address lines to lesser
pins on the chip.
7. The controller multiplexes the
addresses after getting the _____ signal.
a) INTR
b) ACK
c) RESET
d) Request
Answer:
Answer:d
Explanation: The controller gets the request from the device needing the
memory read or write operation and then it multiplexes the address.
8. The RAS and CAS signals are
provided by the ______.
a) Mode register
b) CS
c) Memory controller
d) None of the above
Answer:
Answer:c
Explanation: The multiplexed signal of the controller is split into RAS
and CAS.
9. Consider a memory organised into
8K rows, and that it takes 4 cycles to complete a read opeartion. Then the
refresh overhead of the chip is ______.
a) 0.0021
b) 0.0038
c) 0.0064
d) 0.0128
Answer:
Answer:b
Explanation: The refresh overhead is calculated by taking into account the
total time for refreshing and the interval of each refresh.
10. When DRAM’s are used to build a
complex large memory,then the controller only provides the refresh counter.
a) True
b) False
Answer:
Answer:a
Explanation: None.
Computer Organization Questions and Answers – RamBus Memory
This set of Computer Organisation and Architecture MCQ focuses on
“RamBUS Memory”.
1. RamBUS is better than the other
memory chips in terms of
a) Efficiency.
b) Speed of operation.
c) Wider bandwidth.
d) All of the above.
Answer:
Answer:b
Explanation: The RAMBUS is much advanced mode of memory storage.
2. The key feature of the RAMBUS
tech is ________.
a) Greater memory utilisation
b) Effeciency
c) Speed of transfer
d) None of the above
Answer:
Answer:c
Explanation: The RAMBUS was developed basically to lessen the data
transfer time.
3. The increase in operation speed
is done by
a) Reducing the reference voltage.
b) Increasing the clk frequency.
c) Using enhanced hardware.
d) None of the above.
Answer:
Answer:a
Explanation: The reference voltage is reduced from the Vsupply about 2v.
4. The data is transfered over the
RAMBUS as
a) Packets
b) Blocks
c) Swing voltages
d) Bits
Answer:
Answer:c
Explanation: By using voltage swings to transfer data, transfer rate along
with efficiency is improved.
5. The type of signaling used in
RAMBUS is ______.
a) CLK signalling
b) Differential signalling
c) Integral signalling
d) None of the above
Answer:
Answer:b
Explanation: The differential signaling basically means using voltage
swings to transmit data.
6. The special communication used
in RAMBUS are _________.
a) RAMBUS channel
b) D-link
c) Dial-up
d) None of the above
Answer:
Answer:a
Explanation: The special communication link is used to provide the
necessary deign and required hardware for the transmission.
7. The original design of the
RAMBUS required for ________ data lines.
a) 4
b) 6
c) 8
d) 9
Answer:
Answer:d
Explanation: Out of the 9 data lines, 8 were used for data transmission
and the one left was used for parity checking.
8. The RAMBUS requires specially
designed memory chips similar to _____.
a) SRAM
b) SDRAM
c) DRAM
d) DDRRAM
Answer:
Answer:c
Explanation: The special memory chip should be able to transmit data on
both the edges and is called as RDRAM’s.
9. A RAMBUS which has 18 data lines
is called as _______.
a) Extended RAMBUS
b) Direct RAMBUS
c) Multiple RAMBUS
d) Indirect RAMBUS
Answer:
Answer:b
Explanation: The direct RAMBUS is used to transmit 2 bytes of data at a
time.
10. The RDRAM chips assembled into
larger memory modules called ______.
a) RRIM
b) DIMM
c) SIMM
d) All of the above
Answer:
Answer:a
Explanation: None.
Computer Organization Questions and Answers – Read-Only Memory
This set of Computer Organisation and Architecture MCQ focuses on
“Read-only Memory”.
1. If the transistor gate is
closed, then the ROM stores a value of 1.
a) True
b) False
Answer:
Answer:b
Explanation: If the gate of the transistor is closed then, the value of
zero is stored in the ROM.
2. PROM stands for
a) Programmable Read Only Memory.
b) Pre-fed Read Only Memory.
c) Pre-required Read Only Memory.
d) Programmed Read Only Memory.
Answer:
Answer:a
Explanation: It allows the user to program the ROM.
3. The PROM is more effective than
ROM chips in regard to _______.
a) Cost
b) Memory management
c) Speed of operation
d) Both a and c
Answer:
Answer:d
Explanation: The PROM is cheaper than ROM as they can be programmed
manually.
4. The difference between the EPROM
and ROM circuitory is _____.
a) The usage of MOSFET’s over transistors.
b) The usage of JFET’s over transistors.
c) The usage of an extra transistor.
d) None of the above.
Answer:
Answer:c
Explanation: The EPROM uses an extra transistor where the ground
connection is there in the ROM chip.
5. The ROM chips are mainly used to
store _______.
a) System files
b) Root directories
c) Boot files
d) Driver files
Answer:
Answer:c
Explanation: The ROM chips are used to store boot files required for the
system start up.
6. The contents of the EPROM are
earsed by
a) Overcharging the chip.
b) Exposing the chip to UV rays.
c) Exposing the chip to IR rays.
d) Discharging the Chip.
Answer:
Answer:b
Explanation: To erase the contents of the EPROM the chip is exposed to the
UV rays, which disipate the charge on the transistor.
7. The disadvantage of the EPROM
chip is
a) The high cost factor.
b) The low efficiency.
c) The low speed of operation.
d) The need to remove the chip physically to reprogram it.
Answer:
Answer:d
Explanation: None.
8. EEPROM stands for Electrically
Erasable Programmable Read Only Memory.
a) True
b) False
Answer:
Answer:a
Explanation: The disadvantages of the EPROM led to the development of the
EEPROM.
9. The disadvantage of the EEPROM
is/are
a) The requirement of different voltages to read,write and store information.
b) The Latency inread operation.
c) The inefficient memory mapping schemes used.
d) All of the above.
Answer:
Answer:a
Explanation: None.
10. The memory devices which are
similar to EEPROM but differ in the cost effectiveness is ______.
a) Memory sticks
b) Blue-ray devices
c) Flash memory
d) CMOS
Answer:
Answer:c
Explanation: The flash memory functions similar to the EEPROM but is much
cheaper.
11. The only difference between the
EEPROM and flash memory is that the latter doesn’t allow bulk data to be
written.
a) True
b) False
Answer:
Answer:a
Explanation: This is not permitted as the previous contents of the cells
will be over written.
12. The flash memories find
application in ______.
a) Super computers
b) Mainframe systems
c) Distributed systems
d) Portable devices
Answer:
Answer:d
Explanation: The flash memories low power requirement enables them to be
used in a wide range of hand held devices.
13. The memory module obtained by
placing a number of flash chips for higher memory storage called as _______.
a) FIMM
b) SIMM
c) Flash card
d) RIMM
Answer:
Answer:c
Explanation: None.
14. The flash memory modules
designed to replace the functioning of an harddisk is ______.
a) RIMM
b) Flash drives
c) FIMM
d) DIMM
Answer:
Answer:b
Explanation: The flash drives have been developed to provide faster
operation but with lesser space.
15. The reason for the fast
operating speeds of the flash drives is
a) The absence of any movable parts.
b) The itegarated electronic hardware.
c) The improved bandwidth connection.
d) All of the above.
Answer:
Answer:a
Explanation: Since the flash drives have no movable parts their access and
seeks times are reasonably reduced.
Computer Organization Questions and Answers – Representation of Floating
Number
This set of Computer Organisation and Architecture MCQ focuses on
“Representation Of Floating Numbers”.
1. The decimal numbers represented
in the computer are called as floating point numbers, as the decimal point
floats through the number.
a) True
b) False
Answer:
Answer:a
Explanation: <numeric> By doing this the computer is capable of
accommodating the large float numbers also.
2. The numbers written to the power
of 10 in the representation of decimal numbers are called as _____.
a) Height factors
b) Size factors
c) Scale factors
d) None of the above
Answer:
Answer:c
Explanation: <numeric> These are called as scale factors cause they’re
responsible in determining the degree of specification of a number.
3. If the decimal point is placed
to the right of the first significant digit, then the number is called as
________.
a) Orthogonal
b) Normalized
c) Determinate
d) None of the above
Answer:
Answer:b
Explanation: <numeric> None.
4. ________ constitute the
representation of the floating number.
a) Sign
b) Significant digits
c) Scale factor
d) All of the above
Answer:
Answer:d
Explanation: <numeric> The following factors are responsible for the
representation of the number.
5. The sign followed by the string
of digits is called as ______.
a) Significant
b) Determinant
c) Mantissa
d) Exponent
Answer:
Answer:c
Explanation: <numeric> The mantissa also consists of the decimal point.
6. In IEEE 32-bit representations,
the mantissa of the fraction is said to occupy ______ bits.
a) 24
b) 23
c) 20
d) 16
Answer:
Answer:b
Explanation: <numeric> The mantissa is made to occupy 23 bits, with 8 bit
exponent.
7. The normalized representation of
0.0010110 * 2 ^ 9 is
a) 0 10001000 0010110
b) 0 10000101 0110
c) 0 10101010 1110
d) 0 11110100 11100
Answer:
Answer:b
Explanation: <numeric> Normalized representation is done by shifting the
decimal point.
8. The 32 bit representation of the
decimal number is called as ____.
a) Double-precision
b) Single-precision
c) Extended format
d) None of the above
Answer:
Answer:b
Explanation: <numeric> None.
9. In 32 bit representation the
scale factor as a range of ________.
a) -128 to 127
b) -256 to 255
c) 0 to 255
d) None of the above
Answer:
Answer:a
Explanation: <numeric> Since the exponent field has only 8 bits to store
the value.
10. In double precision format the
size of the mantissa is ______.
a) 32 bit
b) 52 bit
c) 64 bit
d) 72 bit
Answer:
Answer:b
Explanation: <numeric> The double precision format is also called as 64
bit representation
Computer Organization Questions and Answers – Basic Operational Concept
This set of Computer Organization and Architecture MCQ focuses on
“Basic Operational Concept of The Processor”.
1. The decoded instruction is
stored in ______ .
a) IR
b) PC
c) Registers
d) MDR
Answer:
Answer:a
Explanation: The instruction after obtained from the PC, is decoded and
operands are fetched and stored in the IR.
2. The instruction -> Add
LOCA,R0 does,
a) Adds the value of LOCA to R0 and stores in the temp register
b) Adds the value of R0 to the address of LOCA
c) Adds the values of both LOCA and R0 and stores it in R0
d) Adds the value of LOCA with a value in accumulator and stores it in R0
Answer:
Answer:c
Explanation: None.
3. Which registers can interact
with the secondary storage ?
a) MAR
b) PC
c) IR
d) R0
Answer:
Answer:a
Explanation: MAR can interact with secondary storage in order to fetch
data from it.
4. During the execution of a
program which gets initialized first ?
a) MDR
b) IR
c) PC
d) MAR
Answer:
Answer:c
Explanation: For the execution of a process first the instruction is
placed in the PC.
5. Which of the register/s of the
processor is/are connected to Memory Bus ?
a) PC
b) MAR
c) IR
d) Both a and b
Answer:
Answer:b
Explanation: MAR is connected to the memory BUS in order to access the
memory
6. ISP stands for,
a) Instruction Set Processor
b) Information Standard Processing
c) Interchange Standard Protocol
d) Interrupt Service Procedure
Answer:
Answer:a
Explanation: None.
7. The internal Components of the
processor are connected by _______ .
a) Processor intra-connectivity circuitry
b) Processor bus
c) Memory bus
d) Rambus
Answer:
Answer:b
Explanation: The processor BUS is used to connect the various parts in
order to provide a direct connection to the CPU.
8. ______ is used to choose between
incrementing the PC or performing ALU operations .
a) Conditional codes
b) Multiplexer
c) Control unit
d) None of these
Answer:
Answer:b
Explanation: The multiplexer circuit is used to choose between the two as
it can give different results based on the input.
9. The registers,ALU and the
interconnection between them are collectively called as _____ .
a) Process route
b) Information trail
c) information path
d) data path
Answer:
Answer:d
Explanation: The Operational and processing part of the CPU are collectively
called as data path.
10. _______ is used to store data
in registers .
a) D flip flop
b) JK flip flop
c) RS flip flop
d) none of these
Answer:
Answer:a
Explanation: None
Computer Organization Questions and Answers – BUS Structure
This set of Computer Organization and Architecture MCQ focuses on “Bus
Structure”.
1. The main virtue for using single
Bus structure is ,
a) Fast data transfers
b) Cost effective connectivity and speed
c) Cost effective connectivity and ease of attaching peripheral devices
d) None of these
Answer:
Answer:c
Explanation: By using single BUS structure we can minimize the amount
hardware (wire) required and thereby reducing the cost.
2. ______ are used to over come the
difference in data transfer speeds of various devices .
a) Speed enhancing circuitory
b) Bridge circuits
c) Multiple Buses
d) Buffer registers
Answer:
Answer:d
Explanation: By using Buffer registers, the processor sends the data to
the I/O device at the processor speed and the data gets stored in the buffer.After
that the data gets sent to or from the buffer to the devices at the device
speed.
3. To extend the connectivity of
the processor bus we use ______ .
a) PCI bus
b) SCSI bus
c) Controllers
d) Multiple bus
Answer:
Answer:a
Explanation: PCI BUS is used to connect other peripheral devices which
require a direct connection with the processor.
4. IBM developed a bus standard for
their line of computers ‘PC AT’ called _____ .
a) IB bus
b) M-bus
c) ISA
d) None of these
Answer:
Answer:c
Explanation: None.
5. The bus used to connect the
monitor to the CPU is ______ .
a) PCI bus
b) SCSI bus
c) Memory bus
d) Rambus
Answer:
Answer:b
Explanation: SCSI BUS is usually used to connect the video devices to the
processor.
6. ANSI stands for,
a) American National Standards Institute
b) American National Standard Interface
c) American Network Standard Interfacing
d) American Network Security Interrupt
Answer:
Answer:a
Explanation: None.
7. _____ register Connected to the
Processor bus is a single-way transfer capable .
a) PC
b) IR
c) Temp
d) Z
Answer:
Answer:d
Explanation: The Z register is a special register which can interact with
the processor BUS only.
8. In multiple Bus organisation,
the registers are collectively placed and referred as ______ .
a) Set registers
b) Register file
c) Register Block
d) Map registers
Answer:
Answer:b
Explanation: None.
9. The main advantage of multiple
bus organisation over single bus is,
a) Reduction in the number of cycles for execution
b) Increase in size of the registers
c) Better Connectivity
d) None of these
Answer:
Answer:a
Explanation: None.
10. The ISA standard Buses are used
to connect,
a) RAM and processor
b) GPU and processor
c) Harddisk and Processor
d) CD/DVD drives and Processor
Answer:
Answer:c
Explanation: None
Computer Organization Questions and Answers – Bus Arbitration
This set of Computer Organisation and Architecture MCQ focuses on “BUS
Arbitration”.
1. To resolve the clash over the
access of the system BUS we use ______
a) Multiple BUS
b) BUS arbitrator
c) Priority access
d) None of the above
Answer:
Answer:b
Explanation: The BUS arbitrator is used to allow a device to access the
BUS based on certain parameters.
2. The device which is allowed to
initiate data transfers on the BUS at any time is called _____
a) BUS master
b) Processor
c) BUS arbitrator
d) Controller
Answer:
Answer:a
Explanation: The device which is currently accessing the BUS is called as
the BUS master.
3. ______ BUS arbitration appproach
uses the involvement of the processor
a) Centralised arbitration
b) Distributed arbitration
c) Random arbitration
d) All of the above
Answer:
Answer:a
Explanation: In this approach the processor takes into account the various
parameters and assigns the BUS to that device.
4. The circuit used for the request
line is a _________
a) Open-collector
b) EX-OR circuit
c) Open-drain
d) Nand circuit
Answer:
Answer:c
Explanation: None.
5. The Centralised BUS arbitration
is similar to ______ interrupt circuit
a) Priority
b) Parallel
c) Single
d) Daisy chain
Answer:
Answer:d
Explanation: None.
6. When the processor recieves the
request from a device, it responds by sending _____
a) Acknowledge signal
b) BUS grant signal
c) Response signal
d) None of the above
Answer:
Answer:b
Explanation: The Grant signal is passed from one device till the other
until the device that has requested is found.
7. In Centralised Arbitration
______ is/are is the BUS master
a) Processor
b) DMA controller
c) Device
d) Both a and b
Answer:
Answer:d
Explanation: The BUS master is the one that decides which will get the
BUS.
8. Once the BUS is granted to a
device,
a) It activates the BUS busy line
b) Performs the required operation
c) Raises an interrupt
d) All of the above
Answer:
Answer:a
Explanation: The BUS busy activated indicates that the BUS is already
allocated to a device and is being used.
9. The BUS busy line is made of
________
a) Open-drain circuit
b) Open-collector circuit
c) EX-Or circuit
d) Nor circuit
Answer:
Answer:b
Explanation: None.
10. After the device completes its
operation _____ assumes the control of the BUS
a) Another device
b) Processor
c) Controller
d) None of the above
Answer:
Answer:b
Explanation: After the device completes the operation it releases the BUS
and the processor takes over it.
11. The BUS busy line is used
a) To indicate the processor is busy
b) To indicate that the BUS master is busy
c) To indiacate the BUS is already allocated
d) None of the above
Answer:
Answer:c
Explanation: None.
12. Distributed arbitration makes
use of ______
a) BUS master
b) Processor
c) Arbitrator
d) 4-bit ID
Answer:
Answer:d
Explanation: The device uses a 4bit ID number and based on this the BUS is
allocated.
13. In Distributed arbitration, the
device requesting the BUS ______
a) Asserts the Start arbitration signal
b) Sends an interrupt signal
c) Sends an acknowledge signal
d) None of the above
Answer:
Answer:a
Explanation: None.
14. How is a device selected in
Distributed arbitration…??
a) By NANDing the signals passed on all the 4 lines
b) By ANDing the signals passed on all the 4 lines
c) By ORing the signals passed on all the 4 lines
d) None of the above
Answer:
Answer:c
Explanation: The OR output of all the 4 lines is obtained and the device
with the larger value is assigned the BUS.
15. If two devices A and B
contesting for the BUS have ID’s 5 and 6 respectively, which device gets the
BUS based on the Distributed arbitration
a) Device A
b) Device B
c) Insufficient information
Answer:
Answer:b
Explanation: The device Id’s of both the devices are passed on the lines
and since the value of B is greater after the Or operation it gets the BUS.
Computer Organization Questions and Answers – Caches
This set of Computer Organisation and Architecture MCQ focuses on
“Cache’s”.
1. The reason for the
implementation of the cache memory is
a) To increase the internal memory of the system
b) The difference in speeds of operation of the processor and memory
c) To reduce the memory access and cycle time
d) All of the above
Answer:
Answer:b
Explanation: This difference in the speeds of operation of the system
caused it to be inefficient.
2. The effectiveness of the cache
memory is based on the property of ________.
a) Locality of reference
b) Memory localisation
c) Memory size
d) None of the above
Answer:
Answer:a
Explanation: This means that the cache depends on the location in the
memory that is referenced often.
3. The temporal aspect of the
locality of reference means
a) That the recently executed instruction wont be executed soon
b) That the recently executed instruction is temporarily not referenced
c) That the recently executed instruction will be executed soon again
d) None of the above
Answer:
Answer:c
Explanation: None.
4. The spatial aspect of the
locality of reference means
a) That the recently executed instruction is executed again next
b) That the recently executed wont be executed again
c) That the instruction executed will be executed at a later time
d) That the instruction in close proximity of the instruction executed will be
executed in future
Answer:
Answer:d
Explanation: The spatial aspect of locality of reference tells that the
nearby instruction is more likely to be executed in future.
5. The correspondence between the
main memory blocks and those in the cache is given by _________.
a) Hash function
b) Mapping function
c) Locale function
d) Assign function
Answer:
Answer:b
Explanation: The mapping function is used to map the contents of the
memory to the cache.
6. The algorithm to remove and
place new contents into the cache is called _______.
a) Replacement algorithm
b) Renewal algorithm
c) Updation
d) None of the above
Answer:
Answer:a
Explanation: As the cache gets full, older contents of the cache are
swapped out with newer contents. This decision is taken by the algorithm.
7. The write-through procedure is
used
a) To write onto the memory directly
b) To write and read from memory simultaneously
c) To write directly on the memory and the cache simultaneously
d) None of the above
Answer:
Answer:c
Explanation: When write operation is issued then the corresponding
operation is performed.
8. The bit used to signify that the
cache location is updated is ________.
a) Dirty bit
b) Update bit
c) Reference bit
d) Flag bit
Answer:
Answer:a
Explanation: When the cache location is updated in order to signal to the
processor this bit is used.
9. The copy-back protocol is used
a) To copy the contents of the memory onto the cache
b) To update the contents of the memory from the cache
c) To remove the contents of the cache and push it on to the memory
d) None of the above
Answer:
Answer:b
Explanation: This is another way of performing the write operation,wherein
the cache is updated first and then the memory.
10. The approach where the memory
contents are transfered directly to the processor from the memory is called
______.
a) Read-later
b) Read-through
c) Early-start
d) None of the above
Answer:
Answer:c
Explanation: None.
Computer Organization Questions and Answers – Performance Of Caches
This set of Computer Organisation and Architecture MCQ focuses on
“Performance Of Cache”.
1.The key factor/s in commercial
success of a computer is/are ________.
a) Performance
b) Cost
c) Speed
d) Both a and b
Answer:
Answer:d
Explanation: The performance and cost of the computer system is key
decider in the commercial success of the system.
2. The main objective of the
computer system is
a) To provide optimal power operation.
b) To provide best performance at low cost.
c) To provide speedy operation at low power consumption.
d) All of the above.
Answer:--
Answer:--b
Explanation: An optimal system provides best performance at low costs.
3. A common measure of performance
is
a) Price/performance ratio.
b) Performance/price ratio.
c) Operation/price ratio.
d) None of the above.
Answer:--
Answer:--a
Explanation: If this measure is less than one then the system is optimal.
4. The performance depends on
a) The speed of execution only.
b) The speed of fetch and execution.
c) The speed of fetch only
d) The hardware of the system only.
Answer:--
Answer:--b
Explanation: The performance of a system is decided by how quick an
instruction is brought into the system and executed.
5. The main purpose of having
memory hierarchy is to
a) Reduce access time.
b) Provide large capacity.
c) Reduce propagation time.
d) Both a and b.
Answer:--
Answer:--d
Explanation: By using the memory Hierarchy, we can increase the
performance of the system.
6. The memory transfers between two
variable speed devices is always done at the speed of the faster device.
a) True
b) False
Answer:--
Answer:--a
Explanation: None.
7. An effective to introduce
parallelism in memory access is by _______.
a) Memory interleaving
b) TLB
c) Pages
d) Frames
Answer:--
Answer:--a
Explanation: Interleaving divides the memory into modules.
8. The performance of the system is
greatly influenced by increasing the level 1 cache.
a) True
b) False
Answer:--
Answer:--a
Explanation: This is so because the L1 cache is onboard the processor.
9. Two processors A and B have
clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an
instruction with an average
of 3 steps and B can execute with an average of 5 steps.For the execution of
the same instruction which processor is faster
a) A
b) B
C) Both take the same time
d) Insufficient information
Answer:--
Answer:--a
Explanation: None.
10.If the instruction Add R1, R2,
R3 is executed in a system which is pipelined, then the value of S is (Where S
is term of the Basic performance equation)
a) 3
b) ~2
C) ~1
d) 6
Answer:--
Answer:--c
Explanation: Pipelining is a process of fetching an instruction during the
execution of other instruction.
Computer Organization Questions and Answer:--s – Cache Miss and Hit
This set of Computer Organisation and Architecture MCQ focuses on
“Cache Miss and Hit”.
1. The main memory is structured
into modules each with its own address register called ______.
a) ABR
b) TLB
c) PC
d) IR
Answer:--
Answer:--a
Explanation: ABR stands for Address Buffer Register.
2. When consecutive memory
locations are accessed only one module is accessed at a time.
a) True
b) False
Answer:--
Answer:--a
Explanation: In modular approach to memory structuring only one module can
be accessed at a time.
3. In memory interleaving, the
lower order bits of the address is used to
a) Get the data
b) Get the address of the module
c) Get the address of the data within the module
d) None of the above
Answer:--
Answer:--b
Explanation: To implement parallelism in data access we use interleaving.
4. The number successful accesses
to memory stated as a fraction is called as _____.
a) Hit rate
b) Miss rate
c) Success rate
d) Access rate
Answer:--
Answer:--a
Explanation: The hit rate is a important factor in performance
measurement.
5. The number failed attempts to
access memory, stated in the form of fraction is called as _________.
a) Hit rate
b) Miss rate
c) Failure rate
d) Delay rate
Answer:--
Answer:--b
Explanation: The miss rate is key factor in deciding the type of
replacement algorithm.
6. In associative mapping during
LRU, the counter of the new block is set to ‘0’ and all the others are incremented
by one,when _____ occurs.
a) Delay
b) Miss
c) Hit
d) Delayed hit
Answer:--
Answer:--b
Explanation: Miss usually occurs when the memory block requiered is not
present in the cache.
7. In LRU, the refrenced blocks
counter is set to’0′ and that of the previous blocks are incremented by one and
others remain same, in case of ______.
a) Hit
b) Miss
c) Delay
d) None of the above
Answer:--
Answer:--a
Explanation: If the referenced block is present in the memory it is called
as hit.
8. If hit rates are well below 0.9,
then they’re called as speedy computers.
a) True
b) False
Answer:--
Answer:--b
Explanation: It has to be above 0.9 for speedy computers.
9. The extra time needed to bring
the data into memory in case of a miss is called as _____.
a) Delay
b) Propagation time
c) Miss penalty
d) None of the above
Answer:--
Answer:--c
Explanation: None.
10. The miss penalty can be reduced
by improving the mechanisms for data transfer between the different levels of
hierarchy.
a) True
b) False
Answer:--
Answer:--a
Explanation: The extra time needed to bring the data into memory in case
of a miss is called as miss penalty.
Computer Organization Questions and Answer:--s – CISC And RISC
Processors
This set of Computer Organisation and Architecture MCQs focuses on
“CISC And RISC Processors “.
1. The CISC stands for
a) Computer Instruction Set Compliment
b) Complete Instruction Set Compliment
c) Computer Indexed Set Components
d) Complex Instruction set computer
Answer:--
Answer:--d
Explanation: <numeric> CISC is an computer architecture where in the
processor performs more complex operations in one step.
2. The computer architecture aimed
at reducing the time of execution of instructions is ________.
a) CISC
b) RISC
c) ISA
d) ANNA
Answer:--
Answer:--b
Explanation: <numeric> The RISC stands for Reduced Instruction Set
Computer.
3. The Sun micro systems processors
usually follow _____ architecture.
a) CISC
b) ISA
c) ULTRA SPARC
d) RISC
Answer:--
Answer:--d
Explanation: <numeric> The Risc machine aims at reducing the instruction
set of the computer.
4. The RISC processor has a more
complicated design than CISC.
a) True
b) False
Answer:--
Answer:--b
Explanation: <numeric> The RISC processor design is more simpler than
CISC and it consists of fewer transistors.
5. The iconic feature of the RISC
machine among the following are
a) Reduced number of addressing modes
b) Increased memory size
c) Having a branch delay slot
d) All of the above
Answer:--
Answer:--c
Explanation: <numeric> A branch delay slot is an instruction space
immediately following a jump or branch.
6. Both the CISC and RISC
architectures have been developed to reduce the ______.
a) Cost
b) Time delay
c) Semantic gap
d) All of the above
Answer:--
Answer:--c
Explanation: <numeric> The semantic gap is the gap between the high level
language and the low level language.
7. Out of the following which is
not a CISC machine.
a) IBM 370/168
b) VAX 11/780
c) Intel 80486
d) Motorola A567
Answer:--
Answer:--d
Explanation: <numeric> None.
8. Pipe-lining is a unique feature
of _______.
a) RISC
b) CISC
c) ISA
d) IANA
Answer:--
Answer:--a
Explanation: <numeric> The RISC machine architecture was the first to
implement pipe-lining.
9. In CISC architecture most of the
complex instructions are stored in _____.
a) Register
b) Diodes
c) CMOS
d) Transistors
Answer:--
Answer:--d
Explanation: <numeric> In CISC architecture more emphasis is given on the
instruction set and the instructions take over a cycle to complete.
10. Which of the architecture is
power efficient?
a) CISC
b) RISC
c) ISA
d) IANA
Answer:--
Answer:--b
Explanation: <numeric> Hence the RISC architecture is followed in the
design of mobile devices.
Computer Organization Questions and Answer:--s – Direct Memory Access
This set of Computer Organisation and Architecture MCQ focuses on
“Direct Memory Access”.
1. The DMA differs from the
interrupt mode by
a) The involvement of the processor for the operation
b) The method accessing the I/O devices
c) The amount of data transfer possible
d) Both a and c
Answer:--
Answer:--d
Explanation: DMA is an approcah of performing data transfers in bulk
between memory and the external device without the intervention of the
processor.
2. The DMA transfers are performed
by a control circuit called as
a) Device interface
b) DMA controller
c) Data controller
d) Overlooker
Answer:--
Answer:--b
Explanation: The Controller performs the functions that would normally be
carried out by the processor.
3. In DMA transfers, the required
signals and addresses are given by the
a) Processor
b) Device drivers
c) DMA controllers
d) The program itself
Answer:--
Answer:--c
Explanation: The DMA controller acts like a processor for DMA transfers
and overlooks the entire process.
4. After the complition of the DMA
transfer the processor is notified by
a) Acknowledge signal
b) Interrupt signal
c) WMFC signal
d) None of the above
Answer:--
Answer:--b
Explanation: The controller raises an interrupt signal to notify the
processor that the transfer was complete.
5. The DMA controller has _______
registers
a) 4
b) 2
c) 3
d) 1
Answer:--
Answer:--c
Explanation: The Controller uses the registers to store the starting
address,word count and the status of the operation.
6. When the R/W bit of the status
register of the DMA controller is set to 1,
a) Read operation is performed
b) Write operation is performed
Answer:--
Answer:--a
Explanation: None.
7. The controller is connected to
the ____
a) Processor BUS
b) System BUS
c) External BUS
d) None of the above
Answer:--
Answer:--b
Explanation: The controller is directly connected to the system BUS to
provide faster transfer of data.
8. Can a single DMA controller
perform operations on two different disks simulteneously…??
a) True
b) False
Answer:--
Answer:--a
Explanation: The DMA controller can perform operations on two different
disks if the appropriate details are known.
9. The techinique whereby the DMA
controller steals the access cycles of the processor to operate is called
a) Fast conning
b) Memory Con
c) Cycle stealing
d) Memory stealing
Answer:-- Answer:--c
Explanation: The controller takes over the processor’s access cycles and
performs memory operations.
10. The technique where the
controller is given complete access to main memory is
a) Cycle stealing
b) Memory stealing
c) Memory Con
d) Burst mode
Answer:--
Answer:--d
Explanation: The controller is given full control of the memory access
cycles and can transfer blocks at a faster rate.
11. The controller uses _____ to
help with the transfers when handling network interfaces.
a) Input Buffer storage
b) Signal echancers
c) Bridge circuits
d) All of the above
Answer:--
Answer:--a
Explanation: The controller stores the data to transfered in the buffer
and then transfers it.
12. To overcome the conflict over
the possession of the BUS we use ______
a) Optimizers
b) BUS arbitrators
c) Multiple BUS structure
d) None of the above
Answer:--
Answer:--b
Explanation: The BUS arbitrator is used overcome the contention over the
BUS possession.
13. The registers of the controller
are ______
a) 64 bits
b) 24 bits
c) 32 bits
d) 16 bits
Answer:--
Answer:--c
Explanation: None.
14. When process requests for a DMA
transfer ,
a) Then the process is temporarily suspended
b) The process continues execution
c) Another process gets executed
d) Both a and c
Answer:--
Answer:--d
Explanation: The process requesting the transfer is paused and the
operation is performed , meanwhile another process is run on the processor.
15. The DMA transfer is initiated
by _____
a) Processor
b) The process being executed
c) I/O devices
d) OS
Answer:--
Answer:--c
Explanation: The transfer can only be initiated by instruction of a
program being executed.
Computer Organization Questions and Answer:--s – Functional Units of a
Computer
This set of Computer Organization and Architecture MCQ focuses on
“Functional Units of a Computer”.
1. The ______ format is usually
used to store data .
a) BCD
b) Decimal
c) Hecadecimal
d) Octal
Answer:--
Answer:--a
Explanation : The data usually used by computers have to be stored and
represented in a particular format for ease of use.
2. The 8-bit encoding format used
to store data in a computer is ______ .
a) ASCII
b) EBCDIC
c) ANCI
d) USCII
Answer:--
Answer:--b
Explanation: The data to be stored in the computers have to be encoded in
a particular way so as to be provide secure processing of the data.
3. A source program is usually in
_______ .
a) Assembly language
b) Machine level language
c) High-level language
d) Natural language
Answer:--
Answer:--c
Explanation: The program written and before being compiled or assembled is
called as a source program.
4. Which memory device is generally
made of semi-conductors ?
a) RAM
b) Hard-disk
c) Floppy disk
d) Cd disk
Answer:--
Answer:--a
Explanation: Memory devices are usually made of semi conductors for faster
manipulation of the contents.
5. The small extremely fast, RAM’s
are called as _______ .
a) Cache
b) Heaps
c) Accumulators
d) Stacks
Answer:--
Answer:-- : a
Explanation: These small and fast memory devices are compared to RAM
because they optimize the performance of the system and they only keep files
which are required by the current process in them
6. The ALU makes use of _______ to
store the intermediate results .
a) Accumulators
b) Registers
c) Heap
d) Stack
Answer:--
Answer:--a
Explanation: The ALU is the computational center of the CPU. It performs
all the mathematical and logical operations. In order to perform better it uses
some internal memory spaces to store immediate results.
7. The control unit controls other
units by generating ____ .
a) Control signals
b) Timing signals
c) Transfer signals
d) Command Signals
Answer:--
Answer:--b
Explanation: This unit is used to control and coordinate between the
various parts and components of the CPU.
8. ______ are numbers and encoded
characters, generally used as operands .
a) Input
b) Data
c) Information
d) Stored Values
Answer:--
Answer:--b
Explanation: None.
9. The Input devices can send
information to the processor,
a) When the SIN status flag is set
b) When the data arrives regardless of the SIN flag
c) Neither of the cases
d) Either of the cases
Answer:--
Answer:--a
Explanation: The input devices use buffers to store the data received and
when the buffer has some data it sends it to the processor.
10. ______ bus structure is usually
used to connect I/O devices .
a) Single bus
b) Multiple bus
c) Star bus
d) Rambus
Answer:--
Answer:--a
Explanation: BUS is a bunch of wires which carry address,control signals
and data. It is used to connect various components of the computer.
11. The I/O interface required to
connect the I/O device to the bus consists of ______ .
a) Address decoder and registers
b) Control circuits
c) Both a and b
d) Only b
Answer:--
Answer:--c
Explanation: The I/O devices are connected to the CPU via BUS and to
interact with the BUS they’ve a interface.
12. To reduce the memory access
time we generally make use of ______ .
a) Heaps
b) Higher capacity RAM’s
c) SDRAM’s
d) Cache’s
Answer:--
Answer:--d
Explanation: The time required to access a part of the memory for data
retrieval.
13. ______ is generally used to
increase the apparent size of physical memory .
a) Secondary memory
b) Virtual memory
c) Hard-disk
d) Disks
Answer:--
Answer:--b
Explanation: Virtual memory is like an extension to the existing memory.
14. MFC stands for,
a) Memory Format Caches.
b) Memory Function Complete.
c) Memory Find Command.
d) Mass Format Command.
Answer:--
Answer:--b
Explanation: This is a system command enabled when a memory function is
completed by a process.
15. The time delay between two
successive initiation of memory operation _______ .
a) Memory access time
b) Memory search time
c) Memory cycle time
d) Instruction delay
Answer:--
Answer:--c
Explanation: The time taken to finish one task and to start another.
Computer Organization Questions and Answer:--s – Hardwired Control
This set of Computer Organisation and Architecture MCQ focuses on
“Hardwired Control”.
1. ________ are the different
type/s of generating control signals.
a) Micro-programmed
b) Hardwired
c) Micro-instruction
d) Both a and b
Answer:--
Answer:--d
Explanation: <numeric> The above are used to generate control signals in
different types of system architectures.
2. The type of control signal are
generated based on,
a) contents of the step counter
b) Contents of IR
c) Contents of condition flags
d) All of the above
Answer:--
Answer:--d
Explanation: <numeric> Based on the information above the type of control
signal is decided.
3. What does the hardwired control
generator consist of ?
a) Decoder/encoder
b) Condition codes
c) Control step counter
d) All of the above
Answer:--
Answer:--d
Explanation: <numeric> The CU uses the above blocks and IR to produce the
necessary signal.
4. What does the end instruction do
?
a) It ends the generation of a signal
b) It ends the complete generation process
c) It starts a new instruction fetch cycle and resets the counter
d) It is used to shift the control to the processor
Answer:--
Answer:--c
Explanation: <numeric> It is basically used to start the generation of a
new signal.
5. The Zin signal to the processor
is generated using, Zin = T1+T6 ADD + T4 .BR…
a) True
b) False
Answer:--
Answer:--a
Explanation: <numeric> The signal is generated using the logic of the
formula above.
6. What does the RUN signal do ?
a) It causes the termination of a signal
b) It causes a particular signal to perform its operation
c) It causes a particular signal to end
d) It increments the step counter by one
Answer:--
Answer:--d
Explanation: <numeric> The RUN signal increments the step counter by one
for each clock cycle.
7. The name hardwired came because
the sequence of operations carried out are determined by the wiring.
a) True
b) False
Answer:--
Answer:--a
Explanation: <numeric> In other words hardwired is another name for
Hardware Control signal generator.
8. The benefit of using this
approach is
a) It is cost effective
b) It is highly efficient
c) It is very reliable
d) It increases the speed of operation
Answer:--
Answer:--d
Explanation: <numeric> None.
9. The disadvantage/s of the
hardwired approach is
a) It is less flexible
b) It cannot be used for complex instructions
c) It is costly
d) Both a and b
Answer:--
Answer:--d
Explanation: <numeric> The more complex the instruction set less
applicable is hardwired approach.
10. The End signal is generated
using, End = T7.ADD + T5.BR + (T5.N+ T4.-N).BRN…
a) True
b) False
Answer:--
Answer:--a
Explanation: <numeric> None.
Computer Organization Questions and Answer:--s – Microprogrammed
Control
This set of Computer Organisation and Architecture MCQ focuses on
“Micro-programmed Control”.
1. In micro-programmed approach,
the signals are generated by ______.
a) Machine instructions
b) System programs
c) Utility tools
d) None of the above
Answer:--
Answer:--a
Explanation: <numeric> The machine instructions generate the signals.
2. A word whose individual bits
represent a control signal is ______.
a) Command word
b) Control word
c) Co-ordination word
d) Generation word
Answer:--
Answer:--b
Explanation: <numeric> The control word is used to get the different
types of control signals required.
3. A sequence of control words
corresponding to a control sequence is called _______.
a) Micro routine
b) Micro function
c) Micro procedure
d) None of the above
Answer:--
Answer:--a
Explanation: <numeric> The micro routines are used to perform a
particular task.
4. Individual control words of the
micro routine are called as ______.
a) Micro task
b) Micro operation
c) Micro instruction
d) Micro command
Answer:--
Answer:--c
Explanation: <numeric> The each instruction which put together performs
the task.
5. The special memory used to store
the micro routines of a computer is ________.
a) Control table
b) Control store
c) Control mart
d) Control shop
Answer:--
Answer:--b
Explanation: <numeric> The control store is used as a reference to get
the required control routine.
6. To read the control words
sequentially _________ is used.
a) PC
b) IR
c) UPC
d) None of the above
Answer:--
Answer:--c
Explanation: <numeric> The UPC stands for Micro program counter.
7. Every time a new instruction is
loaded into IR the output of ________ is loaded into UPC.
a) Starting address generator
b) Loader
c) Linker
d) Clock
Answer:--
Answer:--a
Explanation: <numeric> The starting address generator is used to load the
address of the next micro instruction.
8. The case/s where
micro-programmed cannot perform well
a) When it requires to check the condition codes
b) When it has to choose between the two alternatives
c) When it is triggered by an interrupt
d) Both a and b
Answer:--
Answer:--d
Explanation: <numeric> None.
9. The signals are grouped such
that mutually exclusive signals are put together.
a) True
b) False
Answer:--
Answer:--a
Explanation: <numeric> This is done to improve the efficiency of the
controller.
10. Highly encoded schemes that use
compact codes to specify a small number of functions in each micro instruction
is ________.
a) Horizontal organisation
b) Vertical organisation
c) Diagonal organisation
d) None of the above
Answer:--
Answer:--b
Explanation: <numeric> None.
Computer Organization Questions and Answer:--s – Hierarchy Of Memory
This set of Computer Organisation and Architecture MCQ focuses on
“Memory Hierarchy”.
1. The standard SRAM chips are
costly as
a) They use highly advanced micro-electronic devices.
b) They house 6 transistor per chip.
c) They require specially designed PCB’s.
d) None of the above.
Answer:--
Answer:--b
Explanation: As they require a large number of transistors, their cost per
bit increases.
2. The drawback of building a large
memory with DRAM is
a) The large cost factor.
b) The inefficient memory organisation.
c) The Slow speed of operation.
d) All of the above.
Answer:--
Answer:--c
Explanation: The DRAM’s were used for large memory modules for a long time
until a substitute was found.
3. To overcome the slow operating
speeds of the secondary memory we make use of faster flash drives.
a) True
b) False
Answer:--
Answer:--a
Explanation: To improve the speed we use flash drives at the cost of
memory space.
4. The fastest data access is
provided using _______.
a) Caches
b) DRAM’s
c) SRAM’s
d) Registers
Answer:--
Answer:--d
Explanation: The fastest data access is provided using registers as these
memory locations are situated inside the processor.
5. The memory which is used to
store the copy of data or instructions stored in larger memories, inside the
CPU is called _______.
a) Level 1 cache
b) Level 2 cache
c) Registers
d) TLB
Answer:--
Answer:--a
Explanation: These memory devices are generally used to map onto the data
stored in the larger memories.
6. The larger memory placed between
the primary cache and the memory is called ______.
a) Level 1 cache
b) Level 2 cache
c) EEPROM
d) TLB
Answer:--
Answer:--b
Explanation: This is basically used to provide effective memory mapping.
7. The next level of memory
hierarchy after the L2 cache is _______.
a) Secondary storage
b) TLB
c) Main memory
d) Register
Answer:--
Answer:--d
Explanation: None.
8. The last on the hierarchy scale
of memory devices is ______.
a) Main memory
b) Secondary memory
c) TLB
d) Flash drives
Answer:--
Answer:--b
Explanation: The secondary memory is the slowest memory device.
9. In the memory hierarchy, as the
speed of operation increases the memory size also increases.
a) True
b) False
Answer:--
Answer:--b
Explanation: As the speed of operation increases the cost increases and
the size decreases.
10. If we use the flash drives
instead of the harddisks, then the secondary storage can go above primary
memory in the hierarchy.
a) True
b) False
Answer:--
Answer:--b
Explanation: The flash drives will increase the speed of transfer but
still it wont be faster than primary memory.
Computer Organization Questions and Answer:--s – Virtual Memory
This set of Computer Organisation and Architecture MCQ focuses on
“Virtual Memory”.
1. The physical memory is not as
large as the address space spanned by the processor.
a) True
b) False
Answer:--
Answer:--a
Explanation: <numeric> This is one of the main reasons for the usage of
virtual memories.
2. The program is divided into
operable parts called as _________.
a) Frames
b) Segments
c) Pages
d) Sheets
Answer:--
Answer:--b
Explanation: <numeric> The program is divided into parts called as
segments for ease of execution.
3. The techniques which move the
program blocks to or from the physical memory is called as ______.
a) Paging
b) Virtual memory organisation
c) Overlays
d) Framing
Answer:--
Answer:--b
Explanation: <numeric> By using this technique the program execution is
accomplished with usage of less space.
4. The binary address issued to
data or instructions are called as ______.
a) Physical address
b) Location
c) Relocatable address
d) Logical address
Answer:--
Answer:--d
Explanation: <numeric> The logical address is the random address
generated by the processor.
5. __________is used to implement
virtual memory organisation.
a) Page table
b) Frame table
c) MMU
d) None of the above
Answer:--
Answer:--c
Explanation: <numeric> The MMU stands for Memory Management Unit.
6. ______ translates logical
address into physical address.
a) MMU
b) Translator
c) Compiler
d) Linker
Answer:--
Answer:--a
Explanation: <numeric> The MMU translates the logical address into
physical address by adding an offset.
7. The main aim of virtual memory
organisation is
a) To provide effective memory access.
b) To provide better memory transfer.
c) To improve the execution of the program.
d) All of the above.
Answer:--
Answer:--d
Explanation: <numeric> None.
8. The DMA doesn’t make use of the
MMU for bulk data transfers.
a) True
b) False
Answer:--
Answer:--b
Explanation: <numeric> The DMA stands for Direct Memory Access,in which a
block of data gets directly transferred from the memory.
9. The virtual memory basically
stores the next segment of data to be executed on the _________.
a) Secondary storage
b) Disks
c) RAM
d) ROM
Answer:--
Answer:--a
Explanation: <numeric> None.
10. The asscociatively mapped
virtual memory makes use of _______.
a) TLB
b) Page table
c) Frame table
d) None of the above
Answer:--
Answer:--a
Explanation: <numeric> TLB stands for Translation Look-aside Buffer.
Computer Organization Questions and Answer:--s – Mapping Functions
This set of Computer Organisation and Architecture MCQ focuses on
“Mapping Functions”.
1. The memory blocks are mapped on
to the cache with the help of ______.
a) Hash functions
b) Vectors
c) Mapping functions
d) None of the above
Answer:--
Answer:--c
Explanation: The mapping functions are used to map the memory blocks on to
their corresponding cache block.
2. During a write operation if the
required block is not present in the cache then ______ occurs.
a) Write latency
b) Write hit
c) Write delay
d) Write miss
Answer:--
Answer:--d
Explanation: This indicates that the operation has missed and it brings
the required block into cache.
3. In ________ protocol the
information is directly written into main memory.
a) Write through
b) Write back
c) Write first
d) None of the above
Answer:--
Answer:--a
Explanation: In case of the miss, then the data gets written directly in
main memory.
4. The only draw back of using the
early start protocol is _______.
a) Time delay
b) Complexity of circuit
c) Latency
d) High miss rate
Answer:--
Answer:--b
Explanation: In this protocol, the required block is read and directly
sent to the processor.
5. The method of mapping the
consecutive memory blocks to consecutive cache blocks is called ______.
a) Set associative
b) Associative
c) Direct
d) Indirect
Answer:--
Answer:--c
Explanation: This method is most simple to implement as it involves direct
mapping of memory blocks.
6. While using the direct mapping
technique, in a 16 bit system the higher order 5 bits is used for ________.
a) Tag
b) Block
c) Word
d) Id
Answer:--
Answer:--a
Explanation: The tag is used to identify the block mapped onto one
particular cache block.
7. In direct mapping the presence
of the block in memory is checked with the help of block field.
a) True
b) False
Answer:--
Answer:--b
Explanation: The tag field is usd to check the presence of a mem block.
8. In associative mapping, in a 16
bit system the tag field has ______ bits.
a) 12
b) 8
c) 9
d) 10
Answer:--
Answer:--a
Explanation: The Tag field is used as an id for the different memory
blocks mapped to the cache.
9. The associative mapping is
costlier than direct mapping.
a) True
b) False
Answer:--
Answer:--a
Explanation: In associative mapping all the tags have to be searched to
find the block.
10. The technique of searching for
a block by going through all the tags is ______.
a) Linear search
b) Binary search
c) Associative search
d) None of the above
Answer:--
Answer:--c
Explanation: None.
11. The set associative map
technique is a combination of the direct and associative technique.
a) True
b) False
Answer:--
Answer:--a
Explanation: The combination of the efficiency of the associative method
and the cheapness of the direct mapping, we get the set-associative mapping.
12. In set-associative technique,
the blocks are grouped into ______ sets.
a) 4
b) 8
c) 12
d) 6
Answer:--
Answer:--d
Explanation: The set-associative technique groups the blocks into
different sets.
13. A control bit called ____ has
to be provided to each blocj in set-associative.
a) Idol bit
b) Valid bit
c) Reference bit
d) All of the above
Answer:--
Answer:--b
Explanation: The valid bit is used to indicate that the block holds valid
information.
14. The bit used to indicate
whether the block was recently used or not is _______.
a) Idol bit
b) Control bit
c) Refernece bit
d) Dirty bit
Answer:--
Answer:--d
Explanation: The dirty bit is used to show that the block was recently
modified and for replacement algorithm.
15. Data which is not up-to date is
called as _______.
a) Spoilt data
b) Stale data
c) Dirty data
d) None of the above
Answer:--
Answer:--b
Explanation: None.
Computer Organization Questions and Answer:--s – Memory Locations and
Addresses
This set of Computer Organization and Architecture MCQ focuses on
“Memory locations and Addresses”.
1. The smallest entity of memory is
called as _______ .
a) Cell
b) Block
c) Instance
d) Unit
Answer:--
Answer:--a
Explanation: Each data is made up of a number units.
2. The collection of the above
mentioned entities where data is stored is called as ______ .
a) Block
B) Set
c) Word
d) Byte
Answer:--
Answer:--c
Explanation: Each readable part of data is called as blocks.
3. An 24 bit address generates an
address space of ______ locations .
a) 1024
b) 4096
c) 2 ^ 48
d) 16,777,216
Answer:--
Answer:--d
Explanation: The number of addressable locations in the system is called
as address space.
4. If a system is 64 bit machine ,
then the length of each word will be ____ .
a) 4 bytes
b) 8 bytes
c) 16 bytes
d) 12 bytes
Answer:--
Answer:--b
Explanation: A 64 bit system means, that at a time 64 bit instruction can
be executed.
5. The type of memory assignment
used in Intel processors is _____ .
a) Little Endian
b) Big Endian
c) Medium Endian
d) None of the above
Answer:--
Answer:--a
Explanation: The method of address allocation to data to be stored is
called as memory assignment.
6. When using the Big Endian
assignment to store a number, the sign bit of the number is stored in _____ .
a) The higher order byte of the word
b) The lower order byte of the word
c) Can’t say
d) None of the above
Answer:--
Answer:--a
Explanation: None.
7. To get the physical address from
the logical address generated by CPU we use ____ .
a) MAR
b) MMU
c) Overlays
d) TLB
Answer:--
Answer:--b
Explanation: Memory Management Unit, is used to add the offset to the
logical address generated by the CPU to get the physical address.
8. _____ method is used to map
logical addresses of variable length onto physical memory.
a) Paging
b) Overlays
c) Segmentation
d) Paging with segmentation
Answer:--
Answer:--c
Explanation: Segmentation is a process in which memory is divided into
groups of variable length called segments.
9. During transfer of data between
the processor and memory we use ______ .
a) Cache
b) TLB
C) Buffers
d) Registers
Answer:--
Answer:--d
Explanation: None.
10. Physical memory is divided into
sets of finite size called as ______ .
a) Frames
b) Pages
c) Blocks
d) Vectors
Answer:--
Answer:--a
Explanation: None.
Computer Organization Questions and Answer:--s – Memory Operations and
Management
This set of Computer Organization and Architecture MCQ focuses on
“Memory Opearions and Management”.
1. Add #%01011101,R1 , when this
instruction is executed then,
a) The binary addition between the operands takes place
b) The Numerical value represented by the binary value is added to the value of
R1
c) The addition doesn’t take place , whereas this is similar to a MOV
instruction
d) None of the above
Answer:--
Answer:--a
Explanation: This performs operations in binary mode directly.
2. If we want to perform memory or
arithmetic operations on data in Hexa-decimal mode then we use ___ symbol
before the operand .
a) ~
b) !
c) $
d) *
Answer:--
Answer:--c
Explanation: None.
3. When generating physical
addresses from logical address the offset is stored in _____ .
a) Translation look-aside buffer
b) Relocation register
c) Page table
d) Shift register
Answer:--
Answer:--b
Explanation: In the MMU the relocation register stores the offset address.
4. The technique used to store
programs larger than the memory is ______ .
a) Overlays
b) Extension registers
c) Buffers
d) Both b and c
Answer:--
Answer:--a
Explanation: In this, only a part of the program getting executed is
stored on the memory and later swapped in for the other part.
5. The unit which acts as an
intermediate agent between memory and backing store to reduce process time is
_____ .
a) TLB’s
b) Registers
c) Page tables
d) Cache
Answer:--
Answer:--d
Explanation: The cache’s help in data transfers by storing most recently
used memory pages.
6. The Load instruction does the
following operation/s,
a) Loads the contents of a disc onto a memory location
b) Loads the contents of a location onto the accumulators
c) Load the contents of the PCB onto the register
d) Both a and c
Answer:--
Answer:--b
Explanation: The load instruction is basically used to load the contents
of a memory location onto a register.
7. Complete the following analogy
:- Registers are to RAM’s as Cache’s are to _____ .
a) System stacks
b) Overlays
c) Page Table
d) TLB
Answer:--
Answer:--d
Explanation: None.
8. The BOOT sector files of the
system are stored in _____ .
a) Harddisk
b) ROM
c) RAM
d) Fast solid state chips in the motherboard
Answer:--
Answer:--b
Explanation: The files which are required for the starting up of a system
are stored on the ROM.
9. The transfer of large chunks of
data with the involvement of the processor is done by _______ .
a) DMA controller
b) Arbitrator
c) User system programs
d) None of the above
Answer:--
Answer:--a
Explanation: This mode of transfer involves the transfer of a large block
of data from the memory.
10. Which of the following
technique/s used to effectively utilize main memory ?
a) Address binding
b) Dynamic linking
c) Dynamic loading
d) Both b and c
Answer:--
Answer:--c
Explanation: In this method only when the routine is required is loaded
and hence saves memory.
Computer Organization Questions and Answer:--s – Numbers and Arithmetic
Operations
This set of Computer Organization and Architecture MCQ focuses on
“Numbers and Arithmetic operation on them”.
1. Which method/s of representation
of numbers occupies large amount of memory than others ?
a) Sign-magnitude
b) 1’s compliment
c) 2’s compliment
d) Both a and b
Answer:--
Answer:-- a
Explanation: It takes more memory as one bit used up to store the sign.
2. Which representation is most
efficient to perform arithmetic operations on the numbers ?
a) Sign-magnitude
b) 1’s compliment
c) 2’S compliment
d) None of the above
Answer:--
Answer:--c
Explanation: The two’s compliment form is more suitable to perform
arithmetic operations as there is no need to involve the sign of the number
into consideration.
3. Which method of representation
has two representations for ‘0’ ?
a) Sign-magnitude
b) 1’s compliment
c) 2’s compliment
d) None of the above
Answer:--
Answer:--a
Explanation: One is positive and one for negative.
4. When we perform subtraction on
-7 and 1 the Answer:-- in 2’s compliment form is _____ .
a) 1010
b) 1110
c) 0110
d) 1000
Answer:--
Answer:--d
Explanation: First the 2’s compliment is found and that is added to the
number and the overflow is ignored.
5. When we perform subtraction on
-7 and -5 the Answer:-- in 2’s compliment form is _____ .
a) 11110
b) 1110
c) 1010
d) 0010
Answer:--
Answer:--b
Explanation: First the 2’s compliment is found and that is added to the
number and the overflow is ignored.
6. When we subtract -3 from 2 , the
Answer:-- in 2’s compliment form is _______ .
a) 0001
b) 1101
c) 0101
d) 1001
Answer:--
Answer:--c
Explanation: First the 2’s compliment is found and that is added to the
number and the overflow is ignored.
7. The processor keeps track of the
results of its operations using a flags called _____ .
a) Conditional code flags
b) Test output flags
c) Type flags
d) None of the above
Answer:--
Answer:--a
Explanation: These flags are used to indicate if there is a overflow or
carry or zero result occurrence.
8. The register used to store the
flags is called as ______ .
a) Flag register
b) Status register
c) Test register
d) Log register
Answer:--
Answer:--b
Explanation: The status register stores the condition codes of the system.
9. The Flag ‘V’ is set to 1
indicates that,
a) The operation is valid
b) The operation is validated
c) The operation as resulted in an overflow
d) Both a and c
Answer:--
Answer:--c
Explanation: This is used to check the overflow occurrence in the
operation.
10. In some pipelined systems, a
different instruction is used to add to numbers which can affect the flags upon
execution. That instruction is _______ .
a) AddSetCC
b) AddCC
c) Add++
d) SumSetCC
Answer:--
Answer:--a
Explanation: By using this instruction the condition flags wont be
affected at all.
11. The most efficient method
followed by computers to multiply two unsigned numbers is _______ .
a) Booth algorithm
b) Bit pair recording of multipliers
c) Restoring algorithm
d) Non restoring algorithm
Answer:--
Answer:--b
Explanation: None.
12. For the addition of large
integers most of the systems make use of ______ .
a) Fast adders
b) Full adders
c) Carry look-ahead adders
d) None of the above
Answer:--
Answer:--c
Explanation: In this method the carries for each step are generated first.
13. In a normal n-bit adder , to
find out if an overflow as occured we make use of _____ .
a) And gate
b) Nand gate
c) Nor gate
d) Xor gate
Answer:--
Answer:--d
Explanation: None.
14. In the implementation of a
Multiplier circuit in the system we make use of _______ .
a) Counter
b) Flip flop
c) Shift register
d) Push down stack
Answer:--
Answer:--c
Explanation: The shift registers are used to store the multiplied Answer:--.
15. When 1101 is used to divide
100010010 the remainder is ______ .
a) 101
b) 11
c) 0
d) 1
Answer:--
Answer:--d
Explanation: None.
Computer Organization Questions and Answer:--s – Performance of a
System
This set of Computer Organization and Architecture MCQ focuses on
“Factors affecting performance of the system and its measurement”.
1. During the execution of the
instructions, a copy of the instructions is placed in the ______ .
a) Register
b) RAM
c) System heap
d) Cache
Answer:--
Answer:--d
Explanation: None.
2. Two processors A and B have
clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an
instruction with an average of 3 steps and B can execute with an average of 5
steps. For the execution of the same instruction which processor is faster ?
a) A
b) B
C) Both take the same time
d) Insuffient information
Answer:--
Answer:--a
Explanation: The performance of a system can be found out using the Basic
performance formula.
3. A processor performing fetch or
decoding of different instruction during the execution of another instruction
is called ______ .
a) Super-scaling
b) Pipe-lining
c) Parallel Computation
d) None of these
Answer:--
Answer:--b
Explanation: Pipe-lining is the process of improving the performance of
the system by processing different instructions at the same time, with only one
instruction performing one specific operation.
4. For a given FINITE number of
instructions to be executed, which architecture of the processor provides for a
faster execution ?
a) ISA
b) ANSA
c) Super-scalar
d) All of the above
Answer:--
Answer:--c
Explanation: In super-scalar architecture, the instructions are set in
groups and they’re decoded and executed together reducing the amount of time
required to process them.
5. The clock rate of the processor
can be improved by,
a) Improving the IC technology of the logic circuits
b) Reducing the amount of processing done in one step
c) By using overclocking method
d) All of the above
Answer:--
Answer:--d
Explanation: The clock rate(frequency of the processor) is the hardware
dependent quantity it is fixed for a given processor.
6. An optimizing Compiler does,
a) Better compilation of the given piece of code.
b) Takes advantage of the type of processor and reduces its process time.
c) Does better memory managament.
d) Both a and c
Answer:--
Answer:--b
Explanation: An optimizing compiler is a compiler designed for the
specific purpose of increasing the operation speed of the processor by reducing
the time taken to compile the program instructions.
7. The ultimate goal of a compiler
is to,
a) Reduce the clock cycles for a programming task.
b) Reduce the size of the object code.
c) Be versatile.
d) Be able to detect even the smallest of errors.
Answer:--
Answer:--a
Explanation: None.
8. SPEC stands for,
a) Standard Performance Evaluation Code.
b) System Processing Enhancing Code.
c) System Performance Evaluation Corporation.
d) Standard Processing Enhancement Corporation.
Answer:--
Answer:--c
Explanation: SPEC is a corporation started to standardize the evaluation
method of a systems performance.
9. As of 2000, the reference system
to find the performance of a system is _____ .
a) Ultra SPARC 10
b) SUN SPARC
c) SUN II
d) None of these
Answer:--
Answer:--a
Explanation: In SPEC system of measuring a systems performance , a system
is used as a reference against which other systems are compared and performance
is determined.
10. When Performing a looping
operation, the instruction gets stored in the ______ .
a) Registers
b) Cache
c) System Heap
d) System stack
Answer:--
Answer:--b
Explanation: When a looping or branching operation is carried out the
offset value is stored in the cache along with the data.
11. The average number of steps
taken to execute the set of instructions can be made to be less than one by
following _______ .
a) ISA
b) Pipe-lining
c) Super-scaling
d) Sequential
Answer:--
Answer:--c
Explanation: The number of steps required to execute a given set of
instructions is sufficiently reduced by using super-scaling. In this method a
set of instructions are grouped together and are processed.
12. If a processor clock is rated
as 1250 million cycles per second, then its clock period is ________ .
a) 1.9 * 10 ^ -10 sec
b) 1.6 * 10 ^ -9 sec
c) 1.25 * 10 ^ -10 sec
d) 8 * 10 ^ -10 sec
Answer:--
Answer:--d
Explanation: None.
13. If the instruction, Add
R1,R2,R3 is executed in a system which is pipe-lined, then the value of S is
(Where S is term of the Basic performance equation)
a) 3
b) ~2
C) ~1
d) 6
Answer:--
Answer:--c
Explanation: S is the number of steps required to execute the
instructions.
14. CISC stands for,
a) Complete Instruction Sequential Compilation
b) Computer Integrated Sequential Compiler
c) Complex Instruction Set Computer
d) Complex Instruction Sequential Compilation
Answer:--
Answer:--c
Explanation: CISC is a type of system architecture where complex
instructions are grouped together and executed to improve the system
performance.
15. As of 2000, the reference
system to find the SPEC rating are built with _____ Processor .
a) Intel Atom SParc 300Mhz
b) Ultra SPARC -IIi 300MHZ
c) Amd Neutrino series
d) ASUS A series 450 Mhz
Answer:--
Answer:--b
Explanation: None.
Computer Organization Questions and Answer:--s – Interrupts
This set of Computer Organisation and Architecture MCQ focuses on
“Interrupts”.
1. The interrupt-request line is a
part of the
a) Data line
b) Control line
c) Address line
d) None
Answer:--
Answer:--b
Explanation: The Interrupt-request line is a control line along which the
device is allowed to send the interrupt signal.
2. The return address from the
interrupt-service routine is stored on the
a) System heap
b) Processor register
c) Processor stack
d) Memory
Answer:--
Answer:--c
Explanation: The Processor after servicing the interrupts as to load the
address of the previous process and this address is stored in the stack.
3. The signal sent to the device from
the processor to the device after recieving an interrupt is
a) Interrupt-acknowledge
b) Return signal
c) Service signal
d) Permission signal
Answer:--
Answer:--a
Explanation: The Processor upon receiving the interrupt should let the
device know that its request is received.
4. When the process is returned
after an interrupt service ______ should be loaded again
i) Register contents
ii) Condition codes
iii) Stack contents
iv) Return addresses
a) i,iv
b) ii,iii and iv
c) iii,iv
d) i,ii
Answer:--
Answer:--d
Explanation: None.
5. The time between the recieval of
an interrupt and its service is ______
a) Interrupt delay
b) Interrupt latency
c) Cycle time
d) Switching time
Answer:--
Answer:--b
Explanation: The delay in servicing of an interrupt happens due to the
time taken for contect switch to take place.
6. Interrupts form an important
part of _____ systems
a) Batch processing
b) Multitasking
c) Real-time processing
d) Multi-user
Answer:--
Answer:--c
Explanation: This forms an imporatant part of the Real time system since
if a process arrives with greater priority then it raises an interrupt and the
other process is stopped and the interrupt will be serviced.
7. A single Interrupt line can be
used to service n different devices
a) True
b) False
Answer:--
Answer:--a
Explanation: None
8. ______ type circuits are
generally used for interrupt service lines
i) open-collector
ii) open-drain
iii) XOR
iv) XNOR
a) i,ii
b) ii
c) ii,iii
d) ii,iv
Answer:--
Answer:--a
Explanation: None
9. The resistor which is attached
to the service line is called _____
a) Push-down resistor
b) Pull-up resistor
c) Break down resistor
d) Line resistor
Answer:--
Answer:--b
Explanation: This resistor is used to pull up the voltage of the interrupt
service line.
10. An interrupt that can be temporarily
ignored is
a) Vectored interrupt
b) Non-maskable interrupt
c) Maskable interrupt
d) High priority interrupt
Answer:--
Answer:--c
Explanation: The maskable interrupts are usually low priority interrupts
which can be ignored if an higher priority process is being executed.
11. The 8085 microprocessor respond
to the presence of an interrupt
a) As soon as the trap pin becomes ‘LOW’
b) By checking the trap pin for ‘high’ status at the end of each instruction
fetch
c) By checking the trap pin for ‘high’ status at the end of execution of each
instruction
d) By checking the trap pin for ‘high’ status at regular intervals
Answer:--
Answer:--c
Explanation: The 8085 microprocessor are designed to complete the
execution of the current instruction and then to service the interrupts.
12. CPU as two modes privileged and
non-privileged. In order to change the mode from privileged to non-privileged
a) A hardware interrupt is needed
b) A software interrupt is needed
c) Either a or b
d) A non-privileged instruction (which does not generate an interrupt)is needed
Answer:--
Answer:--b
Explanation: A software interrupt by some program which needs some cPU
service, at that time the two modes can be interchanged.
13. Which interrupt is
unmaskable…??
a) RST 5.5
b) RST 7.5
c) TRAP
d) Both a and b
Answer:--
Answer:--c
Explanation: The trap is a non-maskable interrupt as it deals with the on
going process in the processor. THe trap is initiated by the process being
executed due to lack of data required for its completion.Hence trap is
unmaskable.
14. From amongst the following
given scenarios determine the right one to justify interrupt mode of data
transfer
i) Bulk transfer of several kilo-byte
ii) Moderately large data transfer of more than 1kb
iii) Short events like mouse action
iv) Keyboard inputs
a) i and ii
b) ii
c) i,ii and iv
d) iv
Answer:--
Answer:--d
Explanation: None.
15. How can the processor ignore
other interrupts when it is servicing one
a) By turning off the interrupt request line
b) By disabling the devices from sending the interrupts
c) BY using edge-triggered request lines
d) All of the above
Answer:--
Answer:--d
Explanation: None.
16. When dealing with multiple
device interrupts , which mechanism is easy to implement
a) Polling method
b) Vectored interrupts
c) Interrupt nesting
d) None of the above
Answer:--
Answer:--a
Explanation: In this method the processor checks the IRQ bits of all the
devices, which ever is enabled first that device is serviced.
17. The interrupt servicing
mechanism in which the reqesting device identifies itself to the processor to
be serviced is
a) Polling
b) Vectored interrupts
c) Interrupt nesting
d) Simultaneous requesting
Answer:--
Answer:--b
Explanation: None.
18. In vectored interrupts, how
does the device indentify itself to the processor..??
a) By sending its device id
b) By sending the machine code for the interrupt service routine
c) By sending the starting address of the service routine
d) Either a or c
Answer:--
Answer:--c
Explanation: By sending the starting address of the routine the device ids
the routine required and thereby identifying itself.
19. The code sent by the device in
vectored interrupt is _____ long
a) upto 16 bits
b) upto 32 bits
c) upto 24 bits
d) 4-8 bits
Answer:--
Answer:--d
Explanation: None.
20. The starting address sent by
the device in vectored interrupt is called as
a) Location id
b) Interrupt vector
c) Service location
d) Service id
Answer:--
Answer:--b
Explanation: None.
21. The processor indicates to the
devices that it is ready to recieve interrupts
a) By enabling the interrupt request line
b) By enabling the IRQ bits
c) By activating the interrupt acknowledge line
d) Either a or b
Answer:--
Answer:--c
Explanation: When the processor activates the acknowledge line the devices
send their interrupts to the processor.
22. We describe a protocol of input
device communication below:
i) Each device has a distinct address.
ii) The BUS controller scans each device in sequence of increasing address
value to determine if the entity wishes to communicate
iii) The device ready to communicate leaves its data in the I/O register
iv) The data is picked up and the controller moves to the step a
Identify the form of communication best describes the I/O mode amongst the
following:
a) Programmed mode of data transfer
b) DMA
c) Interrupt mode
d) Polling
Answer:--
Answer:--d
Explanation: In polling the processor checks each of the device if they
wish to perform data transfer and if they do it performs the particular
operation.
23. Which one of the following is
true with regard to a CPU having a single interrupt request line and single
interrupt grant line…??
i) Neither vectored nor multiple interrupting devices is possible.
ii) Vectored interrupts is not possible but multiple interrupting devices is
possible.
iii) Vectored interrupts is possible and multiple interrupting devices is not
possible.
iv) Both vectored and multiple interrupting devices is possible.
a) iii
b) i,iv
c) ii,iii
d) iii,iv
Answer:--
Answer:--a
Explanation: None.
24. Which table handle stores the
addresses of the interrupt handling sub-routines
a) Interrupt-vector table
b) Vector table
c) Symbol link table
d) None of these
Answer:--
Answer:--a
Explanation: None.
25. _________ method is used to
establish priority by serially connecting all devices that request an
interrupt.
a) Vectored-interrupting
b) Daisy chain
c) Priority
d) Polling
Answer:--
Answer:--b
Explanation: In Daisy chain mechanism, all the devices are connected using
a single request line and they’re serviced based on the interrupting device’s
priority.
26. In daisy chaining device 0 will
pass the signal only if it has..
a) Interrupt request
b) No interrupt request
c) Both a and b
d) None of the above
Answer:--
Answer:--b
Explanation: In daisy chaining since there is only one request line and
only one acknowledge line, the acknowledge signal passes from device to device
until the one with the interrupt is found.
27. ______ interrupt method uses
register whose bits are set seperatedly by interrupt signal for each device:
a) Parallel priority interrupt
b) Serial priority interrupt
c) Daisy chaining
d) None of the above
Answer:--
Answer:--a
Explanation: None.
28. ____ register is used for the
purpose of controlling the status of each interrupt request in parallel
priority interrupt
a) Mass
b) Mark
c) Make
d) Mask
Answer:--
Answer:--d
Explanation: None.
29. The anded output of the bits of
the interrupt register and the mask register are set as input of:
a) Priority decoder
b) Priority encoder
c) Process id encoder
d) Multiplexer
Answer:--
Answer:--b
Explanation: In a parallel priority system, the priority of the device is
obtained by anding the contents of the interrupt register and the mask
register.
30. Interrupts initiated by an
instruction is called as
a) Internal
b) External
c) Hardware
d) Software
Answer:--
Answer:--b
Explanation: None.
Computer Organization Questions and Answer:--s – Pipe-lining
This set of Computer Organisation and Architecture MCQ focuses on
“Pipelining”.
1. ______ have been developed
specifically for pipelined systems.
a) Utility softwares
b) Speed up utilities
c) Optimizing compilers
d) None of the mentioned
Answer:--
Answer:--c
Explanation: <numeric> The compilers which are designed to remove
redundant parts of the code are called as optimizing compilers.
2. The pipelining process is also
called as ______.
a) Superscalar operation
b) Assembly line operation
c) Von neumann cycle
d) None of the mentioned
Answer:--
Answer:--b
Explanation: <numeric> It is called so because it performs its operation
at assembly level.
3. The fetch and execution cycles
are interleaved with the help of ________.
a) Modification in processor architecture
b) Clock
c) Special unit
d) Control unit
Answer:--
Answer:--b
Explanation: <numeric> The time cycle of the clock is adjusted to perform
the interleaving.
4. Each stage in pipelining should
be completed within ____ cycle.
a) 1
b) 2
c) 3
d) 4
Answer:--
Answer:--a
Explanation: <numeric> The stages in the pipelining should get completed
within one cycle to increase the speed of performance.
5.In pipelining the task which
requires the least time is performed first.
a) True
b) False
Answer:--
Answer:--b
Explanation: <numeric> This is done to avoid starvation of the longer
task.
6. If a unit completes its task
before the allotted time period, then
a) It’ll perform some other task in the remaining time
b) Its time gets reallocated to different task
c) It’ll remain idle for the remaining time
d) None of the mentioned
Answer:--
Answer:--c
Explanation: <numeric> None.
7. To increase the speed of memory
access in pipelining, we make use of _______.
a) Special memory locations
b) Special purpose registers
c) Cache
d) Buffers
Answer:--
Answer:--c
Explanation: <numeric> By using the cache we can reduce the speed of
memory access by a factor of 10.
8. The periods of time when the
unit is idle is called as _____.
a) Stalls
b) Bubbles
c) Hazards
d) Both a and b
Answer:--
Answer:--d
Explanation: <numeric> The stalls are a type of hazards that affect a
pipelined system.
9. The contention for the usage of
a hardware device is called as ______.
a) Structural hazard
b) Stalk
c) Deadlock
d) None of the mentioned
Answer:--
Answer:--a
Explanation: <numeric> None.
10. The situation where in the data
of operands are not available is called ______.
a) Data hazard
b) Stock
c) Deadlock
d) Structural hazard
Answer:--
Answer:--a
Explanation: <numeric> Data hazards are generally caused when the data is
not ready on the destination side.
Computer Organization Questions and Answer:--s – Standard I/O
Interfaces
This set of Computer Organisation and Architecture MCQ focuses on
“Standard I/O Interfaces”.
1. ______ is used as an
intermediate to extend the processor BUS.
a) Bridge
b) Router
c) Connector
d) Gateway
Answer:--
Answer:--a
Explanation: The bridge circuit is basically used to extend the processor
BUS to connect devices.
2. ________ is an extension of the
processor BUS.
a) SCSI BUS
b) USB
c) PCI BUS
d) None of the above
Answer:--
Answer:--c
Explanation: The PCI BUS is used as an extension of the processor BUS and
devices connected to it, is like connected to the Processor itself.
3. ISA stands for
a) International American Standard.
b) Industry Standard Architecture.
c) International Standard Architecture.
d) None of the above.
Answer:--
Answer:--b
Explanation: The ISA is a architectural standard developed by IBM for its
PC’s.
4. ANSI stands for
a) American National Standards Institute.
b) Architectural National Standards Institute.
c) Asian National Standards Institute.
d) None of the above.
Answer:--
Answer:--a
Explanation: The ANSI is one of the standard architecture used by
companies in designing the systems.
5. The video devices are connected
to ______ BUS.
a) PCI
b) USB
c) HDMI
d) SCSI
Answer:--
Answer:--d
Explanation: The SCSI BUS is used to connect the video devices to
processor by providing a parallel BUS.
6. SCSI stands for
a) Signal Computer System Interface.
b) Small Computer System Interface.
c) Small Coding System Interface.
d) Signal Coding System Interface.
Answer:--
Answer:--b
Explanation: The SCSI BUS is used to connect disks and video controllers.
7. ISO stands for
a) International Standards Organisation.
b) International Software Organisation.
c) Industrial Standards organisation.
d) Industrial Software Organisation.
Answer:--
Answer:--a
Explanation: The ISO is yet another architectural standard, used to design
systems.
8. The system developed by IBM with
ISA architecture is ______.
a) SPARC
b) SUN-SPARC
c) PC-AT
d) None of the above
Answer:--
Answer:--c
Explanation: None.
9. IDE disk is connected to the PCI
BUS using ______ interface.
a) ISA
b) ISO
c) ANSI
d) IEEE
Answer:--
Answer:--a
Explanation: None.
10. IDE stands for
a) Intergrated Device Electronics.
b) International Device Encoding.
c) Industrial Decoder Electronics.
d) International Decoder Encoder.
Answer:--
Answer:--a
Explanation: The IDE interface is used to connect the harddisk to the
processor in most of the Pentium processors.
Computer Organization Questions and Answer:--s – Static Memories
This set of Computer Organisation and Architecture MCQ focuses on
“Static Memories”.
1. The duration between the read
and the mfc signal is ______.
a) Access time
b) Latency
c) Delay
d) Cycle time
Answer:--
Answer:--a
Explanation: The time between the issue of read signal and the completion
of it is called memory access time.
2. The minimum time delay between
two successive memory read operations is ______.
a) Cycle time
b) Latency
c) Delay
d) None of the above
Answer:--
Answer:--a
Explanation: The Time taken by the cpu to end one read operation and to
start one more is cycle time.
3. MFC is used to
a) Issue a read signal.
b) Signal to the device that the memory read operation is complete.
c) Signal the processor the memory operation is complete.
d) Assign a device to perform the read operation.
Answer:--
Answer:--c
Explanation: The MFC stands for memory Function Complete.
4. __________ is the bootleneck,
when it comes computer performance.
a) Memory access time
b) Memory cycle time
c) Delay
d) Latency
Answer:--
Answer:--b
Explanation: The processor can execute instructions faster than they’re
fetched, hence cycle time is the bottleneck for performance.
5. The logical addresses generated
by the cpu are mapped onto physical memory by ____.
a) Relocation register
b) TLB
c) MMU
d) None of the above
Answer:--
Answer:--c
Explanation: The MMU stands for memory management unit, which is used to
map logical address onto phsical address.
6. VLSI stands for
a) Very Large Scale Integration.
b) Very Large Stand-alone Integration.
c) Volatile Layer System Interface.
d) None of the above.
Answer:--
Answer:--a
Explanation: None.
7. The cells in a row are connected
to a common line called ______.
a) Work line
b) Word line
c) Length line
d) Principle diagonal
Answer:--
Answer:--b
Explanation: This means that the cell contents together form one word of
instruction or data.
8. The cells in each column are
connected to ______.
a) Word line
b) Data line
c) Read line
d) Sense/ Write line
Answer:--
Answer:--d
Explanation: The cells in each column are connected to the sense/write
circuit using two bit lines and which is inturn connected to the data lines.
9. The word line is driven by the
_____.
a) Chip select
b) Address decoder
c) Data line
d) Control line
Answer:--
Answer:--b
Explanation: None.
10. A 16 X 8 organisation of memory
cells, can store upto _____.
a) 256 bits
b) 1024 bits
c) 512 bits
d) 128 bits
Answer:--
Answer:--d
Explanation: It can store upto 128 bits as each cell can hold one bit of
data.
11. A memory organisation that can
hold upto 1024 bits and has a minimum of 10 address lines can be organised into
_____.
a) 128 X 8
b) 256 X 4
c) 512 X 2
d) 1024 X 1
Answer:--
Answer:--d
Explanation: All the others require less than 10 address bits.
12. Circuits that can hold their
state as long as power is applied is _______.
a) Dynamic memory
b) Static memory
c) Register
d) Cache
Answer:--
Answer:--b
Explanation: None.
13. The number of external
connections required in 16 X 8 memory organisation is _____.
a) 14
b) 19
c) 15
d) 12
Answer:--
Answer:--a
Explanation: In the 14, 8-data lines,4-address lines and 2 are sense/write
and CS signals.
14. The advantage of CMOS SRAM over
the transistor one’s is
a) Low cost.
b) High efficiency.
c) High durability.
d) Low power consumption.
Answer:--
Answer:--d
Explanation: This is because the cell consumes power only when it is being
accessed.
15. In a 4M-bit chip organisation
has a total of 19 external connections.then it has _______ address if 8 data
lines are there.
a) 10
b) 8
c) 9
d) 12
Answer:--
Answer:--c
Explanation: To have 8 data lines and 19 external connections it has to
have 9 address lines(i.e 512 x 8 organisation).
Computer Organization Questions and Answer:--s – Instructions and
Instruction Sequencing
This set of Computer Organization and Architecture MCQ focuses on
“Instructions and Instruction Sequencing”.
1. RTN stands for,
a) Register Transfer Notation
b) Register Transmission Notation
c) Regular Transmission Notation
d) Regular Transfer Notation
Answer:--
Answer:--a
Explanation: This is the way of writing the assembly language code with
the help of register notations.
2. The instruction, Add Loc,R1 in
RTN is _______ .
a) AddSetCC Loc+R1
b) R1=Loc+R1
c) Not possible to write in RTN
d) R1<-[Loc]+[R1] [expand title="Answer:--"] Answer:--d Explanation: None.
[/expand]
3. Can you perform addition on
three operands simultaneously in ALN using Add instruction ?
a) Yes
b) Not possible using Add, we’ve to use AddSetCC
c) Not permitted
d) None of the above
Answer:--
Answer:--c
Explanation: You cannot perform addition on three operands simultaneously
because the third operand is where the result is stored.
4. The instruction, Add R1,R2,R3 in
RTN is _______ .
a) R3=R1+R2+R3
b) R3<-[R1]+[R2]+[R3] c) R3=[R1]+[R2] d) R3<-[R1]+[R2] [expand
title="Answer:--"] Answer:--d Explanation: In RTN the first
operand is the destination and the second operand is the source. [/expand]
5. In a system, which has 32
registers the register id is ____ long .
a) 16 bits
b) 8 bits
c) 5 bits
d) 6 bits
Answer:--
Answer:--c
Explanation: The ID is the name tag given to each of the registers and
used to identify them.
6. The two phases of executing an
instruction are,
a) Instruction decoding and storage
b) Instruction fetch and instruction execution
c) Instruction execution and storage
d) Instruction fetch and Instruction processing
Answer:--
Answer:--b
Explanation: First, the instructions are fetched and decoded and then
they’re executed and stored.
7. The Instruction fetch phase ends
with,
a) Placing the data from the address in MAR into MDR
b) Placing the address of the data into MAR
c) Completing the execution of the data and placing its storage address into
MAR
d) Decoding the data in MDR and placing it in IR
Answer:--
8. While using the iterative
construct (Branching) in execution, ____ instruction is used to check the
condition .
a) TestAndSet
b) Branch
c) TestCondn
d) None of the above
Answer:--
Answer:--b
Explanation: Branch instruction is used to check the test condition and to
perform the memory jump with help of offset.
9. When using Branching, the usual
sequencing of the PC is altered. A new instruction is loaded which is called as
______ .
a) Branch target
b) Loop target
c) Forward target
d) Jump instruction
Answer:--
Answer:--a
Explanation: None.
10. The condition flag Z is set to
1 to indicate,
a) The operation has resulted in an error
b) The operation requires an interrupt call
c) The result is zero
d) There is no empty register available
Answer:--
Answer:--c
Explanation: This condition flag is used to check if the arithmetic
operation yields a zero output.
