Cache Miss and Hit

Computer Organization Questions and Answers – Cache Miss and Hit

This set of Computer Organisation and Architecture MCQ focuses on “Cache Miss and Hit”.

1. The main memory is structured into modules each with its own address register called ______.
a) ABR
b) TLB
c) PC
d) IR
View Answer

Answer:a
Explanation: ABR stands for Address Buffer Register.

2. When consecutive memory locations are accessed only one module is accessed at a time.
a) True
b) False
View Answer

Answer:a
Explanation: In modular approach to memory structuring only one module can be accessed at a time.

3. In memory interleaving, the lower order bits of the address is used to
a) Get the data
b) Get the address of the module
c) Get the address of the data within the module
d) None of the above
View Answer

Answer:b
Explanation: To implement parallelism in data access we use interleaving.

4. The number successful accesses to memory stated as a fraction is called as _____.
a) Hit rate
b) Miss rate
c) Success rate
d) Access rate
View Answer

Answer:a
Explanation: The hit rate is a important factor in performance measurement.

5. The number failed attempts to access memory, stated in the form of fraction is called as _________.
a) Hit rate
b) Miss rate
c) Failure rate
d) Delay rate
View Answer

Answer:b
Explanation: The miss rate is key factor in deciding the type of replacement algorithm.

6. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one,when _____ occurs.
a) Delay
b) Miss
c) Hit
d) Delayed hit
View Answer

Answer:b
Explanation: Miss usually occurs when the memory block requiered is not present in the cache.

7. In LRU, the refrenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in case of ______.
a) Hit
b) Miss
c) Delay
d) None of the above
View Answer

Answer:a
Explanation: If the referenced block is present in the memory it is called as hit.

8. If hit rates are well below 0.9, then they’re called as speedy computers.
a) True
b) False
View Answer

Answer:b
Explanation: It has to be above 0.9 for speedy computers.

9. The extra time needed to bring the data into memory in case of a miss is called as _____.
a) Delay
b) Propagation time
c) Miss penalty
d) None of the above
View Answer

Answer:c
Explanation: None.

10. The miss penalty can be reduced by improving the mechanisms for data transfer between the different levels of hierarchy.
a) True
b) False
View Answer

Answer:a
Explanation: The extra time needed to bring the data into memory in case of a miss is called as miss penalty.

Mapping Functions

Computer Organization Questions and Answers – Mapping Functions

This set of Computer Organisation and Architecture MCQ focuses on “Mapping Functions”.

1. The memory blocks are mapped onto the cache with the help of ______.
a) Hash functions
b) Vectors
c) Mapping functions
d) None of the above
View Answer

Answer:c
Explanation: The mapping functions are used to map the memory blocks on to their corresponding cache block.

2. During a write operation if the required block is not present in the cache then ______ occurs.
a) Write latency
b) Write hit
c) Write delay
d) Write miss
View Answer

Answer:d
Explanation: This indicates that the operation has missed and it brings the required block into cache.

3. In ________ protocol the information is directly written into main memory.
a) Write through
b) Write back
c) Write first
d) None of the above
View Answer

Answer:a
Explanation: In case of the miss, then the data gets written directly in main memory.

4. The only draw back of using the early start protocol is _______.
a) Time delay
b) Complexity of circuit
c) Latency
d) High miss rate
View Answer

Answer:b
Explanation: In this protocol, the required block is read and directly sent to the processor.

5. The method of mapping the consecutive memory blocks to consecutive cache blocks is called ______.
a) Set associative
b) Associative
c) Direct
d) Indirect
View Answer

Answer:c
Explanation: This method is most simple to implement as it involves direct mapping of memory blocks.

6. While using the direct mapping technique, in a 16 bit system the higher order 5 bits is used for ________.
a) Tag
b) Block
c) Word
d) Id
View Answer

Answer:a
Explanation: The tag is used to identify the block mapped onto one particular cache block.

7. In direct mapping the presence of the block in memory is checked with the help of block field.
a) True
b) False
View Answer

Answer:b
Explanation: The tag field is usd to check the presence of a mem block.

8. In associative mapping, in a 16 bit system the tag field has ______ bits.
a) 12
b) 8
c) 9
d) 10
View Answer

Answer:a
Explanation: The Tag field is used as an id for the different memory blocks mapped to the cache.

9. The associative mapping is costlier than direct mapping.
a) True
b) False
View Answer

Answer:a
Explanation: In associative mapping all the tags have to be searched to find the block.

10. The technique of searching for a block by going through all the tags is ______.
a) Linear search
b) Binary search
c) Associative search
d) None of the above
View Answer

Answer:c
Explanation: None.

11. The set associative map technique is a combination of the direct and associative technique.
a) True
b) False
View Answer

Answer:a
Explanation: The combination of the efficiency of the associative method and the cheapness of the direct mapping, we get the set-associative mapping.

12. In set-associative technique, the blocks are grouped into ______ sets.
a) 4
b) 8
c) 12
d) 6
View Answer

Answer:d
Explanation: The set-associative technique groups the blocks into different sets.

13. A control bit called ____ has to be provided to each blocj in set-associative.
a) Idol bit
b) Valid bit
c) Reference bit
d) All of the above
View Answer

Answer:b
Explanation: The valid bit is used to indicate that the block holds valid information.

14. The bit used to indicate whether the block was recently used or not is _______.
a) Idol bit
b) Control bit
c) Refernece bit
d) Dirty bit
View Answer

Answer:d
Explanation: The dirty bit is used to show that the block was recently modified and for replacement algorithm.

15. Data which is not up-to date is called as _______.
a) Spoilt data
b) Stale data
c) Dirty data
d) None of the above
View Answer

Answer:b
Explanation: None.

Create Your Own Programming Language

Hierarchy Of Memory

Computer Organization Questions and Answers – Heirarchy Of Memory

This set of Computer Organisation and Architecture MCQ focuses on “Memory Hierarchy”.

1. The standard SRAM chips are costly as
a) They use highly advanced micro-electronic devices.
b) They house 6 transistor per chip.
c) They require specially designed PCB’s.
d) None of the above.
View Answer

Answer:b
Explanation: As they require a large number of transistors, their cost per bit increases.

2. The drawback of building a large memory with DRAM is
a) The large cost factor.
b) The inefficient memory organisation.
c) The Slow speed of operation.
d) All of the above.
View Answer

Answer:c
Explanation: The DRAM’s were used for large memory modules for a long time until a substitute was found.

3. To overcome the slow operating speeds of the secondary memory we make use of faster flash drives.
a) True
b) False
View Answer

Answer:a
Explanation: To improve the speed we use flash drives at the cost of memory space.

4. The fastest data access is provided using _______.
a) Caches
b) DRAM’s
c) SRAM’s
d) Registers
View Answer

Answer:d
Explanation: The fastest data access is provided using registers as these memory locations are situated inside the processor.

5. The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called _______.
a) Level 1 cache
b) Level 2 cache
c) Registers
d) TLB
View Answer

Answer:a
Explanation: These memory devices are generally used to map onto the data stored in the larger memories.

6. The larger memory placed between the primary cache and the memory is called ______.
a) Level 1 cache
b) Level 2 cache
c) EEPROM
d) TLB
View Answer

Answer:b
Explanation: This is basically used to provide effective memory mapping.

7. The next level of memory hierarchy after the L2 cache is _______.
a) Secondary storage
b) TLB
c) Main memory
d) Register
View Answer

Answer:d
Explanation: None.

8. The last on the hierarchy scale of memory devices is ______.
a) Main memory
b) Secondary memory
c) TLB
d) Flash drives
View Answer

Answer:b
Explanation: The secondary memory is the slowest memory device.

9. In the memory hierarchy, as the speed of operation increases the memory size also increases.
a) True
b) False
View Answer

Answer:b
Explanation: As the speed of operation increases the cost increases and the size decreases.

10. If we use the flash drives instead of the harddisks, then the secondary storage can go above primary memory in the hierarchy.
a) True
b) False
View Answer

Answer:b
Explanation: The flash drives will increase the speed of transfer but still it wont be faster than primary memory.

Cache Memory

Computer Organization Questions and Answers – Caches

This set of Computer Organisation and Architecture MCQ focuses on “Cache’s”.

1. The reason for the implementation of the cache memory is
a) To increase the internal memory of the system
b) The difference in speeds of operation of the processor and memory
c) To reduce the memory access and cycle time
d) All of the above
View Answer

Answer:b
Explanation: This difference in the speeds of operation of the system caused it to be inefficient.

2. The effectiveness of the cache memory is based on the property of ________.
a) Locality of reference
b) Memory localisation
c) Memory size
d) None of the above
View Answer

Answer:a
Explanation: This means that the cache depends on the location in the memory that is referenced often.

3. The temporal aspect of the locality of reference means
a) That the recently executed instruction wont be executed soon
b) That the recently executed instruction is temporarily not referenced
c) That the recently executed instruction will be executed soon again
d) None of the above
View Answer

Answer:c
Explanation: None.

4. The spatial aspect of the locality of reference means
a) That the recently executed instruction is executed again next
b) That the recently executed wont be executed again
c) That the instruction executed will be executed at a later time
d) That the instruction in close proximity of the instruction executed will be executed in future
View Answer

Answer:d
Explanation: The spatial aspect of locality of reference tells that the nearby instruction is more likely to be executed in future.

5. The correspondence between the main memory blocks and those in the cache is given by _________.
a) Hash function
b) Mapping function
c) Locale function
d) Assign function
View Answer

Answer:b
Explanation: The mapping function is used to map the contents of the memory to the cache.

6. The algorithm to remove and place new contents into the cache is called _______.
a) Replacement algorithm
b) Renewal algorithm
c) Updation
d) None of the above
View Answer

Answer:a
Explanation: As the cache gets full, older contents of the cache are swapped out with newer contents. This decision is taken by the algorithm.

7. The write-through procedure is used
a) To write onto the memory directly
b) To write and read from memory simultaneously
c) To write directly on the memory and the cache simultaneously
d) None of the above
View Answer

Answer:c
Explanation: When write operation is issued then the corresponding operation is performed.

8. The bit used to signify that the cache location is updated is ________.
a) Dirty bit
b) Update bit
c) Reference bit
d) Flag bit
View Answer

Answer:a
Explanation: When the cache location is updated in order to signal to the processor this bit is used.

9. The copy-back protocol is used
a) To copy the contents of the memory onto the cache
b) To update the contents of the memory from the cache
c) To remove the contents of the cache and push it on to the memory
d) None of the above
View Answer

Answer:b
Explanation: This is another way of performing the write operation,wherein the cache is updated first and then the memory.

10. The approach where the memory contents are transfered directly to the processor from the memory is called ______.
a) Read-later
b) Read-through
c) Early-start
d) None of the above
View Answer

Answer:c
Explanation: None.

Computer Organization Questions and Answers – Pipe-lining

This set of Computer Organisation and Architecture MCQ focuses on “Pipelining”.

1. ______ have been developed specifically for pipelined systems.
a) Utility software
b) Speed up utilities
c) Optimizing compilers
d) None of the mentioned
View Answer

Answer:c
Explanation: <numeric> The compilers which are designed to remove redundant parts of the code are called as optimizing compilers.

2. The pipelining process is also called as ______.
a) Superscalar operation
b) Assembly line operation
c) Von neumann cycle
d) None of the mentioned
View Answer

Answer:b
Explanation: <numeric> It is called so because it performs its operation at assembly level.

3. The fetch and execution cycles are interleaved with the help of ________.
a) Modification in processor architecture
b) Clock
c) Special unit
d) Control unit
View Answer

Answer:b
Explanation: <numeric> The time cycle of the clock is adjusted to perform the interleaving.

4. Each stage in pipelining should be completed within ____ cycle.
a) 1
b) 2
c) 3
d) 4
View Answer

Answer:a
Explanation: <numeric> The stages in the pipelining should get completed within one cycle to increase the speed of performance.

5.In pipelining the task which requires the least time is performed first.
a) True
b) False
View Answer

Answer:b
Explanation: <numeric> This is done to avoid starvation of the longer task.

6. If a unit completes its task before the allotted time period, then
a) It’ll perform some other task in the remaining time
b) Its time gets reallocated to different task
c) It’ll remain idle for the remaining time
d) None of the mentioned
View Answer

Answer:c
Explanation: <numeric> None.

7. To increase the speed of memory access in pipelining, we make use of _______.
a) Special memory locations
b) Special purpose registers
c) Cache
d) Buffers
View Answer

Answer:c
Explanation: <numeric> By using the cache we can reduce the speed of memory access by a factor of 10.

8. The periods of time when the unit is idle is called as _____.
a) Stalls
b) Bubbles
c) Hazards
d) Both a and b
View Answer

Answer:d
Explanation: <numeric> The stalls are a type of hazards that affect a pipelined system.

9. The contention for the usage of a hardware device is called as ______.
a) Structural hazard
b) Stalk
c) Deadlock
d) None of the mentioned
View Answer

Answer:a
Explanation: <numeric> None.

10. The situation where in the data of operands are not available is called ______.
a) Data hazard
b) Stock
c) Deadlock
d) Structural hazard
View Answer

Answer:a
Explanation: <numeric> Data hazards are generally caused when the data is not ready on the destination side.

for more 

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Addressing Modes”.

1. The instruction, MOV AX, 0005H belongs to the address mode
a) register
b) direct
c) immediate
d) register relative
View Answer

Answer: c
Explanation: In Immediate addressing mode, immediate data is a part of instruction and appears in the form of successive byte or bytes.

2. The instruction, MOV AX, 1234H is an example of
a) register addressing mode
b) direct addressing mode
c) immediate addressing mode
d) based indexed addressing mode
View Answer

Answer: c
Explanation: since immediate data is present in the instruction.

3. The instruction, MOV AX, [2500H] is an example of
a) immediate addressing mode
b) direct addressing mode
c) indirect addressing mode
d) register addressing mode
View Answer

Answer: b
Explanation: Since the address is directly specified in the instruction as a part of it.

4. If the data is present in a register and it is referred using the particular register, then it is
a) direct addressing mode
b) register addressing mode
c) indexed addressing mode
d) immediate addressing mode
View Answer

Answer: b
Explanation: Since register is used to refer the address.

5. The instruction, MOV AX,[BX] is an example of
a) direct addressing mode
b) register addressing mode
c) register relative addressing mode
d) register indirect addressing mode
View Answer

Answer: d
Explanation: Since the register used to refer the address is accessed indirectly.

6. If the offset of the operand is stored in one of the index registers, then it is
a) based indexed addressing mode
b) relative based indexed addressing mode
c) indexed addressing mode
d) none of the mentioned
View Answer

Answer: c
Explanation: in indexed addressing mode, the offset of operand is stored and in the rest of them, address is stored.

7. The addressing mode that is used in unconditional branch instructions is
a) intrasegment direct addressing mode
b) intrasegment indirect addressing mode
c) intrasegment direct and indirect addressing mode
d) intersegment direct addressing mode
View Answer

Answer: b
Explanation: In intrasegment indirect mode, the branch address is found as the content of a register or a memory location.

8. If the location to which the control is to be transferred lies in a different segment other than the current one, then the mode is called
a) intrasegment mode
b) intersegment direct mode
c) intersegment indirect mode
d) intersegment direct and indirect mode
View Answer

Answer: d
Explanation: In intersegment mode, the control to be transferred lies in a different segment.

9. The instruction, JMP 5000H:2000H;
is an example of
a) intrasegment direct mode
b) intrasegment indirect mode
c) intersegment direct mode
d) intersegment indirect mode
View Answer

Answer: c
Explanation: since in intersegment direct mode, the address to which the control is to be transferred is in a different segment.

10. The contents of a base register are added to the contents of index register in
a) indexed addressing mode
b) based indexed addressing mode
c) relative based indexed addressing mode
d) based indexed and relative based indexed addressing mode
View Answer

Answer: d
Explanation: The effective address is formed by adding the contents of both base and index registers to a default segment

Computer Organization Questions and Answers – Basic Operational Concept

This set of Computer Organization and Architecture MCQ focuses on “Basic Operational Concept of The Processor”.

1. The decoded instruction is stored in ______ .
a) IR
b) PC
c) Registers
d) MDR
View Answer

Answer:  a
Explanation: The instruction after obtained from the PC, is decoded and operands are fetched and stored in the IR.

2. The instruction -> Add LOCA,R0 does,
a) Adds the value of LOCA to R0 and stores in the temp register
b) Adds the value of R0 to the address of LOCA
c) Adds the values of both LOCA and R0 and stores it in R0
d) Adds the value of LOCA with a value in accumulator and stores it in R0
View Answer

Answer: c
Explanation: None.

3. Which registers can interact with the secondary storage ?
a) MAR
b) PC
c) IR
d) R0
View Answer

Answer: a
Explanation: MAR can interact with secondary storage in order to fetch data from it.

4. During the execution of a program which gets initialized first ?
a) MDR
b) IR
c) PC
d) MAR
View Answer

Answer: c
Explanation: For the execution of a process first the instruction is placed in the PC.

5. Which of the register/s of the processor is/are connected to Memory Bus ?
a) PC
b) MAR
c) IR
d) Both a and b
View Answer

Answer: b
Explanation: MAR is connected to the memory BUS in order to access the memory

6. ISP stands for,
a) Instruction Set Processor
b) Information Standard Processing
c) Interchange Standard Protocol
d) Interrupt Service Procedure
View Answer

Answer: a
Explanation: None.

7. The internal Components of the processor are connected by _______ .
a) Processor intra-connectivity circuitry
b) Processor bus
c) Memory bus
d) Rambus
View Answer

Answer: b
Explanation: The processor BUS is used to connect the various parts in order to provide a direct connection to the CPU.

8. ______ is used to choose between incrementing the PC or performing ALU operations .
a) Conditional codes
b) Multiplexer
c) Control unit
d) None of these
View Answer

Answer: b
Explanation: The multiplexer circuit is used to choose between the two as it can give different results based on the input.

9. The registers,ALU and the interconnection between them are collectively called as _____ .
a) Process route
b) Information trail
c) information path
d) data path
View Answer

Answer: d
Explanation: The Operational and processing part of the CPU are collectively called as data path.

10. _______ is used to store data in registers .
a) D flip flop
b) JK flip flop
c) RS flip flop
d) none of these
View Answer

Answer: a
Explanation: None.